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Searched refs:DMA_CTR1_DDW_LOG2 (Results 1 – 25 of 55) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_sram.c692 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Read_DMA()
794 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Write_DMA()
Dstm32u5xx_hal_ospi.c1427 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Transmit_DMA()
1608 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Receive_DMA()
Dstm32u5xx_hal_xspi.c1591 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1776 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
Dstm32u5xx_hal_dma_ex.c3951 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_sram.c691 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Read_DMA()
793 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Write_DMA()
Dstm32n6xx_hal_sdram.c741 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Read_DMA()
845 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Write_DMA()
Dstm32n6xx_hal_xspi.c1471 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1656 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
Dstm32n6xx_hal_dma_ex.c3972 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_sram.c692 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Read_DMA()
794 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Write_DMA()
Dstm32h5xx_hal_sdram.c742 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Read_DMA()
846 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Write_DMA()
Dstm32h5xx_hal_xspi.c1444 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1629 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
Dstm32h5xx_hal_dma_ex.c3952 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_sram.c691 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Read_DMA()
793 … = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SRAM_Write_DMA()
Dstm32h7rsxx_hal_sdram.c741 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Read_DMA()
845 …= hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_SDRAM_Write_DMA()
Dstm32h7rsxx_hal_xspi.c1464 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1649 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
Dstm32h7rsxx_hal_dma_ex.c3912 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h744 #define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWo…
1938 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
2453 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, in LL_DMA_SetDestDataWidth()
2488 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); in LL_DMA_GetDestDataWidth()
Dstm32h7rsxx_hal_dma.h455 #define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord…
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h1415 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
1924 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, in LL_DMA_SetDestDataWidth()
1950 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); in LL_DMA_GetDestDataWidth()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h768 #define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWo…
2360 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
3269 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, in LL_DMA_SetDestDataWidth()
3304 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); in LL_DMA_GetDestDataWidth()
Dstm32n6xx_hal_dma.h680 #define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord…
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h2054 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2564 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, in LL_DMA_SetDestDataWidth()
2590 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); in LL_DMA_GetDestDataWidth()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h1970 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2656 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, in LL_DMA_SetDestDataWidth()
2690 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); in LL_DMA_GetDestDataWidth()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_dma_ex.c3638 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2281 #define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary log… macro

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