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Searched refs:DMA_CLLR_UT1 (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h749 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
2991 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConfigLinkUpdate()
3014 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_EnableCTR1Update()
3036 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_DisableCTR1Update()
3058 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) in LL_DMA_IsEnabledCTR1Update()
3059 == (DMA_CLLR_UT1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR1Update()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h930 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4701 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_EnableCTR1Update()
4723 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_DisableCTR1Update()
4745 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) in LL_DMA_IsEnabledCTR1Update()
4746 == (DMA_CLLR_UT1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR1Update()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h941 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4797 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_EnableCTR1Update()
4827 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_DisableCTR1Update()
4857 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) in LL_DMA_IsEnabledCTR1Update()
4858 == (DMA_CLLR_UT1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR1Update()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h924 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4617 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_EnableCTR1Update()
4647 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_DisableCTR1Update()
4677 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) in LL_DMA_IsEnabledCTR1Update()
4678 == (DMA_CLLR_UT1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR1Update()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h977 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
5904 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5935 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_EnableCTR1Update()
5965 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); in LL_DMA_DisableCTR1Update()
5995 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) in LL_DMA_IsEnabledCTR1Update()
5996 == (DMA_CLLR_UT1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCTR1Update()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c852 …pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CL… in LL_DMA_CreateLinkNode()
880 … (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3834 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4015 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4080 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1125 …pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CL… in LL_DMA_CreateLinkNode()
1158 … (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4208 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4224 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4406 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4471 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1079 …pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CL… in LL_DMA_CreateLinkNode()
1111 … (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4209 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4225 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4407 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4472 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1131 …pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CL… in LL_DMA_CreateLinkNode()
1160 … (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4166 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4348 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4413 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_dma.c1195 …pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CL… in LL_DMA_CreateLinkNode()
1229 … (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ in LL_DMA_ConnectLinkNode()
Dstm32n6xx_hal_dma_ex.c4229 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4245 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4427 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4492 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2371 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32wba52xx.h2956 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32wba54xx.h3139 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32wba5mxx.h3139 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32wba55xx.h3139 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h4011 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32h523xx.h5373 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
Dstm32h562xx.h5816 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6461 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5168 #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update tra… macro

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