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Searched refs:DMA_CLLR_USA (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h755 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
2991 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConfigLinkUpdate()
3215 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
3237 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
3259 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
3260 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h936 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4902 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
4924 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
4946 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
4947 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h947 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5070 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
5100 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
5130 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
5131 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h930 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4890 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
4920 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
4950 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
4951 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h983 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
5904 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
6208 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
6238 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
6268 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
6269 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c853 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
881 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3834 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4015 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4080 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1126 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1159 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4208 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4224 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4406 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4471 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1080 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1112 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4209 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4225 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4407 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4472 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1132 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1161 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4166 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4348 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4413 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_dma.c1196 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1230 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32n6xx_hal_dma_ex.c4229 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4245 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4427 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4492 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2362 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba52xx.h2947 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba54xx.h3130 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba5mxx.h3130 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba55xx.h3130 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h4002 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h523xx.h5364 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h562xx.h5807 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6452 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5159 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro

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