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Searched refs:DMA_CLLR_UDA (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h757 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
2991 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConfigLinkUpdate()
3282 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_EnableCDARUpdate()
3304 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_DisableCDARUpdate()
3326 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) in LL_DMA_IsEnabledCDARUpdate()
3327 == (DMA_CLLR_UDA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCDARUpdate()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h938 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4969 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_EnableCDARUpdate()
4991 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_DisableCDARUpdate()
5013 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) in LL_DMA_IsEnabledCDARUpdate()
5014 == (DMA_CLLR_UDA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCDARUpdate()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h949 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5161 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_EnableCDARUpdate()
5191 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_DisableCDARUpdate()
5221 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) in LL_DMA_IsEnabledCDARUpdate()
5222 == (DMA_CLLR_UDA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCDARUpdate()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h932 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4981 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_EnableCDARUpdate()
5011 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_DisableCDARUpdate()
5041 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) in LL_DMA_IsEnabledCDARUpdate()
5042 == (DMA_CLLR_UDA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCDARUpdate()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h985 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
5904 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
6299 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_EnableCDARUpdate()
6329 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); in LL_DMA_DisableCDARUpdate()
6359 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) in LL_DMA_IsEnabledCDARUpdate()
6360 == (DMA_CLLR_UDA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCDARUpdate()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c854 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
881 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3834 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4016 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4081 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1127 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1159 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4208 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4224 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4407 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4472 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1081 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1112 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4209 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4225 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4408 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4473 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1133 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1161 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4166 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4349 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4414 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_dma.c1197 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1230 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32n6xx_hal_dma_ex.c4229 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4245 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4428 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4493 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2359 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32wba52xx.h2944 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32wba54xx.h3127 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32wba5mxx.h3127 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32wba55xx.h3127 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3999 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32h523xx.h5361 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
Dstm32h562xx.h5804 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6449 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5156 #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update des… macro

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