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Searched refs:DMA_CLLR_UB1 (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h753 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
2991 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConfigLinkUpdate()
3148 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_EnableCBR1Update()
3170 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_DisableCBR1Update()
3192 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) in LL_DMA_IsEnabledCBR1Update()
3193 == (DMA_CLLR_UB1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCBR1Update()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h934 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4835 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_EnableCBR1Update()
4857 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_DisableCBR1Update()
4879 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) in LL_DMA_IsEnabledCBR1Update()
4880 == (DMA_CLLR_UB1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCBR1Update()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h945 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4979 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_EnableCBR1Update()
5009 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_DisableCBR1Update()
5039 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) in LL_DMA_IsEnabledCBR1Update()
5040 == (DMA_CLLR_UB1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCBR1Update()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h928 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4799 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_EnableCBR1Update()
4829 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_DisableCBR1Update()
4859 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) in LL_DMA_IsEnabledCBR1Update()
4860 == (DMA_CLLR_UB1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCBR1Update()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h981 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
5904 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
6117 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_EnableCBR1Update()
6147 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); in LL_DMA_DisableCBR1Update()
6177 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) in LL_DMA_IsEnabledCBR1Update()
6178 == (DMA_CLLR_UB1)) ? 1UL : 0UL); in LL_DMA_IsEnabledCBR1Update()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c853 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
881 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3834 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4015 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4080 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1126 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1159 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4208 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4224 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4406 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4471 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1080 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1112 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4209 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4225 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4407 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4472 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1132 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1161 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4166 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4348 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4413 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_dma.c1196 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1230 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32n6xx_hal_dma_ex.c4229 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4245 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4427 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4492 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2365 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32wba52xx.h2950 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32wba54xx.h3133 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32wba5mxx.h3133 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32wba55xx.h3133 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h4005 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32h523xx.h5367 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
Dstm32h562xx.h5810 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6455 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5162 #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update blo… macro

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