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Searched refs:DMA1_Ch4_7_DMAMUX1_OVR_IRQn (Results 1 – 6 of 6) sorted by relevance

/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g050xx.h87 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator
Dstm32g070xx.h87 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator
Dstm32g051xx.h88 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator
Dstm32g061xx.h88 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator
Dstm32g071xx.h89 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator
Dstm32g081xx.h89 …DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interru… enumerator