/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/ |
D | stm32l0xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 70 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/ |
D | stm32g4xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE) 57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 61 (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE) 73 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/ |
D | stm32f1xx_ll_dma.h | 48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/ |
D | stm32f0xx_ll_dma.h | 48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 69 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/ |
D | stm32f2xx_ll_dma.h | 48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/ |
D | stm32f7xx_ll_dma.h | 48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/ |
D | stm32l4xx_ll_dma.h | 51 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 56 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 70 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/ |
D | stm32l5xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), 56 (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/ |
D | stm32f4xx_ll_dma.h | 48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/ |
D | stm32u0xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
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/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/ |
D | stm32g0xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/ |
D | stm32f3xx_ll_dma.h | 48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/ |
D | stm32l1xx_ll_dma.h | 48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/ |
D | stm32mp1xx_ll_dma.h | 48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/ |
D | stm32h7xx_ll_dma.h | 49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
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/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/ |
D | stm32wlxx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
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/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/ |
D | stm32c0xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 56 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l041xx.h | 533 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 534 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 535 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 536 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 537 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 538 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 539 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 540 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 541 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 588 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l010x8.h | 494 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 495 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 496 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 497 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 498 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 499 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 500 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 501 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 502 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 546 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l010xb.h | 496 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 497 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 498 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 499 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 500 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 501 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 502 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 503 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 504 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 550 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l031xx.h | 514 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 515 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 516 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 517 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 518 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 519 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 520 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 521 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 522 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 568 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l051xx.h | 542 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 543 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 544 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 545 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 546 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 547 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 548 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 549 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 550 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 602 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l010x6.h | 494 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 495 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 496 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 497 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 498 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 499 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 500 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 501 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 502 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 545 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l081xx.h | 576 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 577 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 578 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 579 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 580 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 581 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 582 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 583 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 584 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 643 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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D | stm32l071xx.h | 557 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) macro 558 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 559 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 560 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 561 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 562 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 563 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 564 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 565 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 623 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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