Searched refs:DCMIPP_P0FCTCR_FRATE_Pos (Results 1 – 10 of 10) sorted by relevance
329 #define DCMIPP_FRAME_RATE_1_OVER_2 (1U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 2 captured */330 #define DCMIPP_FRAME_RATE_1_OVER_4 (2U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 4 captured */331 #define DCMIPP_FRAME_RATE_1_OVER_8 (3U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 8 captured */
640 #define DCMIPP_FRAME_RATE_1_OVER_2 (1U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 2 captured */641 #define DCMIPP_FRAME_RATE_1_OVER_4 (2U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 4 captured */642 #define DCMIPP_FRAME_RATE_1_OVER_8 (3U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 8 captured */
4502 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro4503 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */
5026 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro5027 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */
4947 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro4948 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */
4579 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro4580 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */
9052 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro9053 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0…
9994 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro9995 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0…
9752 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro9753 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0…
9294 #define DCMIPP_P0FCTCR_FRATE_Pos (0U) macro9295 #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0…
