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Searched refs:DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g473xx.h3023 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
3024 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
Dstm32g483xx.h3244 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
3245 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
Dstm32g474xx.h3153 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
3154 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
Dstm32g484xx.h3374 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
3375 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l471xx.h16177 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
16178 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l475xx.h16341 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
16342 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l476xx.h16498 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
16499 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l486xx.h16717 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
16718 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l485xx.h16566 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
16567 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4a6xx.h18064 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
18065 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l496xx.h17724 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
17725 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4r5xx.h18098 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
18099 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4r7xx.h18597 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
18598 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4s5xx.h18445 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
18446 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4s7xx.h18944 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
18945 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4p5xx.h19135 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
19136 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
Dstm32l4q5xx.h19646 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
19647 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h4537 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
4538 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
Dstm32l562xx.h4869 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
4870 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x0…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h4536 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
4537 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
Dstm32h562xx.h4955 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
4956 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
Dstm32h533xx.h4945 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
4946 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h5621 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
5622 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
Dstm32u535xx.h5221 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
5222 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
Dstm32u575xx.h5624 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) macro
5625 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)

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