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Searched refs:CPUCR (Results 1 – 25 of 35) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_pwr.h1186 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); in LL_PWR_CPU_SetD1PowerMode()
1199 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); in LL_PWR_CPU_SetCDPowerMode()
1228 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); in LL_PWR_CPU_GetD1PowerMode()
1240 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); in LL_PWR_CPU_GetCDPowerMode()
1269 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); in LL_PWR_CPU_SetD2PowerMode()
1298 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); in LL_PWR_CPU_GetD2PowerMode()
1327 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); in LL_PWR_CPU_SetD3PowerMode()
1340 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); in LL_PWR_CPU_SetSRDPowerMode()
1369 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); in LL_PWR_CPU_GetD3PowerMode()
1381 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); in LL_PWR_CPU_GetSRDPowerMode()
[all …]
Dstm32h7xx_hal_pwr.h386 ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\
387 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
389 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
391 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
393 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
410 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
411 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
412 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
413 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
427 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_pwr_ex.c753 SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); in HAL_PWREx_EnterSTOP2Mode()
756 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); in HAL_PWREx_EnterSTOP2Mode()
846 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWREx_EnterSTOPMode()
910 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); in HAL_PWREx_EnterSTOPMode()
921 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); in HAL_PWREx_EnterSTOPMode()
930 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); in HAL_PWREx_EnterSTOPMode()
1011 SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); in HAL_PWREx_EnterSTANDBYMode()
1033 SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); in HAL_PWREx_EnterSTANDBYMode()
1065 SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); in HAL_PWREx_EnterSTANDBYMode()
1091 MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); in HAL_PWREx_ConfigD3Domain()
[all …]
Dstm32h7xx_hal_pwr.c633 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTOPMode()
638 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTOPMode()
642 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTOPMode()
646 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); in HAL_PWR_EnterSTOPMode()
697 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTANDBYMode()
703 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTANDBYMode()
708 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); in HAL_PWR_EnterSTANDBYMode()
712 SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); in HAL_PWR_EnterSTANDBYMode()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_pwr.h617 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
629 return READ_BIT(PWR->CPUCR, PWR_CPUCR_SVOS); in LL_PWR_GetStopModeRegulVoltageScaling()
642 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS, PDMode); in LL_PWR_SetPowerDownModeDS()
654 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS)); in LL_PWR_GetPowerDownModeDS()
1515 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
1525 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1635 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); in LL_PWR_ClearFlag_STOP_SB()
Dstm32n6xx_hal_pwr.h345 …((__FLAG__) == PWR_FLAG_SBF) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) …
346 …((__FLAG__) == PWR_FLAG_STOPF) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) …
369 … ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \
370 … ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \
371 (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)))
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_pwr.c603 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS); in HAL_PWR_EnterSTOPMode()
651 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS); in HAL_PWR_EnterSTANDBYMode()
Dstm32n6xx_hal_pwr_ex.c368 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling); in HAL_PWREx_ControlStopModeVoltageScaling()
378 return (PWR->CPUCR & PWR_CPUCR_SVOS); in HAL_PWREx_GetStopModeVoltageRange()
Dstm32n6xx_ll_pwr.c65 WRITE_REG(PWR->CPUCR, 0x00010000U); in LL_PWR_DeInit()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h1062 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h7b0xx.h1065 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h7b0xxq.h1066 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h7a3xxq.h1063 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h7b3xx.h1065 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h7b3xxq.h1066 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h730xxq.h1223 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h733xx.h1222 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h725xx.h1220 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h730xx.h1222 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h735xx.h1223 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h742xx.h1129 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h723xx.h1219 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h750xx.h1217 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h753xx.h1217 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member
Dstm32h745xx.h1262 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ member

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