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Searched refs:CPU2CR (Results 1 – 10 of 10) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_pwr.h1214 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); in LL_PWR_CPU2_SetD1PowerMode()
1254 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); in LL_PWR_CPU2_GetD1PowerMode()
1284 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); in LL_PWR_CPU2_SetD2PowerMode()
1312 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); in LL_PWR_CPU2_GetD2PowerMode()
1355 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); in LL_PWR_CPU2_SetD3PowerMode()
1395 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); in LL_PWR_CPU2_GetD3PowerMode()
1407 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); in LL_PWR_HoldCPU1()
1417 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); in LL_PWR_ReleaseCPU1()
1427 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); in LL_PWR_IsCPU1Held()
1491 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); in LL_PWR_CPU2_EnableD3RunInLowPowerMode()
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Dstm32h7xx_hal_pwr.h385 ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\
388 ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\
390 ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\
392 ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\
394 ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\
503 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_pwr_ex.c885 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); in HAL_PWREx_EnterSTOPMode()
926 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); in HAL_PWREx_EnterSTOPMode()
1015 SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); in HAL_PWREx_EnterSTANDBYMode()
1047 SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); in HAL_PWREx_EnterSTANDBYMode()
1069 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); in HAL_PWREx_EnterSTANDBYMode()
1120 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); in HAL_PWREx_ClearDomainFlags()
1127 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); in HAL_PWREx_ClearDomainFlags()
1150 if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) in HAL_PWREx_HoldCore()
1166 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); in HAL_PWREx_HoldCore()
1202 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); in HAL_PWREx_ReleaseCore()
Dstm32h7xx_hal_pwr.c698 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); in HAL_PWR_EnterSTANDBYMode()
704 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); in HAL_PWR_EnterSTANDBYMode()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h745xx.h1263 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member
Dstm32h745xg.h1263 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member
Dstm32h755xx.h1264 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member
Dstm32h757xx.h1345 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member
Dstm32h747xg.h1344 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member
Dstm32h747xx.h1344 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ member