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Searched refs:CLLR (Results 1 – 25 of 54) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h4677 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, in LL_DMA_ConfigLinkUpdate()
4701 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR1Update()
4723 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR1Update()
4745 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR1Update()
4768 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR2Update()
4790 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR2Update()
4812 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR2Update()
4835 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCBR1Update()
4857 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCBR1Update()
4879 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCBR1Update()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h4765 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, in LL_DMA_ConfigLinkUpdate()
4797 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR1Update()
4827 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR1Update()
4857 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR1Update()
4888 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR2Update()
4918 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR2Update()
4948 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR2Update()
4979 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCBR1Update()
5009 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCBR1Update()
5039 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCBR1Update()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h4585 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, in LL_DMA_ConfigLinkUpdate()
4617 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR1Update()
4647 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR1Update()
4677 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR1Update()
4708 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR2Update()
4738 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR2Update()
4768 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR2Update()
4799 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCBR1Update()
4829 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCBR1Update()
4859 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCBR1Update()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h2990 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, in LL_DMA_ConfigLinkUpdate()
3014 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR1Update()
3036 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR1Update()
3058 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR1Update()
3081 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR2Update()
3103 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR2Update()
3125 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR2Update()
3148 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCBR1Update()
3170 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCBR1Update()
3192 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCBR1Update()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h5903 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, in LL_DMA_ConfigLinkUpdate()
5935 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR1Update()
5965 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR1Update()
5995 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR1Update()
6026 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCTR2Update()
6056 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCTR2Update()
6086 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCTR2Update()
6117 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_U… in LL_DMA_EnableCBR1Update()
6147 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR… in LL_DMA_DisableCBR1Update()
6177 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, … in LL_DMA_IsEnabledCBR1Update()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma.c497 hdma->Instance->CLLR = 0U; in HAL_DMA_DeInit()
1163 if (hdma->Instance->CLLR == 0U) in HAL_DMA_IRQHandler()
1731 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_Init()
Dstm32h7rsxx_hal_dma_ex.c718 hdma->Instance->CLLR = 0U; in HAL_DMAEx_List_DeInit()
837 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start()
916 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start_IT()
3679 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_List_Init()
Dstm32h7rsxx_ll_dma.c382 LL_DMA_WriteReg(tmp, CLLR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_dma.c367 hdma->Instance->CLLR = 0U; in HAL_DMA_DeInit()
1042 if (hdma->Instance->CLLR == 0U) in HAL_DMA_IRQHandler()
1657 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_Init()
Dstm32wbaxx_hal_dma_ex.c683 hdma->Instance->CLLR = 0U; in HAL_DMAEx_List_DeInit()
805 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start()
884 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start_IT()
3507 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_List_Init()
Dstm32wbaxx_ll_dma.c292 LL_DMA_WriteReg(tmp, CLLR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma.c372 hdma->Instance->CLLR = 0U; in HAL_DMA_DeInit()
1054 if (hdma->Instance->CLLR == 0U) in HAL_DMA_IRQHandler()
1685 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_Init()
Dstm32h5xx_hal_dma_ex.c722 hdma->Instance->CLLR = 0U; in HAL_DMAEx_List_DeInit()
851 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start()
930 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start_IT()
3695 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_List_Init()
Dstm32h5xx_hal_dcmi.c1288 tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA; in DCMI_DMAXferCplt()
Dstm32h5xx_ll_dma.c347 LL_DMA_WriteReg(tmp, CLLR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma.c415 hdma->Instance->CLLR = 0U; in HAL_DMA_DeInit()
1089 if (hdma->Instance->CLLR == 0U) in HAL_DMA_IRQHandler()
1789 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_Init()
Dstm32n6xx_hal_dma_ex.c726 hdma->Instance->CLLR = 0U; in HAL_DMAEx_List_DeInit()
855 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start()
934 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start_IT()
3715 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_List_Init()
Dstm32n6xx_hal_dcmi.c1288 tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA; in DCMI_DMAXferCplt()
Dstm32n6xx_ll_dma.c399 LL_DMA_WriteReg(tmp, CLLR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma.c365 hdma->Instance->CLLR = 0U; in HAL_DMA_DeInit()
1047 if (hdma->Instance->CLLR == 0U) in HAL_DMA_IRQHandler()
1666 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_Init()
Dstm32u5xx_hal_dma_ex.c722 hdma->Instance->CLLR = 0U; in HAL_DMAEx_List_DeInit()
851 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start()
930 hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; in HAL_DMAEx_List_Start_IT()
3696 WRITE_REG(hdma->Instance->CLLR, 0U); in DMA_List_Init()
Dstm32u5xx_hal_dcmi.c1288 tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA; in DCMI_DMAXferCplt()
Dstm32u5xx_ll_dma.c350 LL_DMA_WriteReg(tmp, CLLR, 0U); in LL_DMA_DeInit()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h290 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset:… member
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h417 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: … member

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