Home
last modified time | relevance | path

Searched refs:C2MR (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_ipcc.h429 CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos); in LL_C2_IPCC_EnableTransmitChannel()
452 SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos)); in LL_C2_IPCC_DisableTransmitChannel()
475 …return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)… in LL_C2_IPCC_IsEnabledTransmitChannel()
498 CLEAR_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_EnableReceiveChannel()
521 SET_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_DisableReceiveChannel()
544 return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C2_IPCC_IsEnabledReceiveChannel()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_ipcc.h429 CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos); in LL_C2_IPCC_EnableTransmitChannel()
452 SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos)); in LL_C2_IPCC_DisableTransmitChannel()
475 …return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)… in LL_C2_IPCC_IsEnabledTransmitChannel()
498 CLEAR_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_EnableReceiveChannel()
521 SET_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_DisableReceiveChannel()
544 return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C2_IPCC_IsEnabledReceiveChannel()
Dstm32wlxx_hal_ipcc.h182 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
183 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
210 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
211 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_ipcc.h429 CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos); in LL_C2_IPCC_EnableTransmitChannel()
452 SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos)); in LL_C2_IPCC_DisableTransmitChannel()
475 …return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)… in LL_C2_IPCC_IsEnabledTransmitChannel()
498 CLEAR_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_EnableReceiveChannel()
521 SET_BIT(IPCCx->C2MR, Channel); in LL_C2_IPCC_DisableReceiveChannel()
544 return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C2_IPCC_IsEnabledReceiveChannel()
Dstm32mp1xx_hal_ipcc.h181 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
182 ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
209 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
210 ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h657 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb1mxx.h673 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb30xx.h656 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb35xx.h765 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb55xx.h803 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb5mxx.h803 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h663 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wb15xx.h673 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h570 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wl54xx.h570 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32wl55xx.h570 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h2431 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151fxx_cm4.h2445 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151axx_ca7.h2431 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151axx_cm4.h2397 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151dxx_cm4.h2397 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151cxx_ca7.h2479 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151cxx_cm4.h2445 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp151fxx_ca7.h2479 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member
Dstm32mp153axx_ca7.h2532 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, … member

12