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Searched refs:C1MR (Results 1 – 25 of 42) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
360 CLEAR_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_EnableReceiveChannel()
383 SET_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_DisableReceiveChannel()
406 return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C1_IPCC_IsEnabledReceiveChannel()
Dstm32wbxx_hal_ipcc.h167 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
168 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
188 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
189 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
360 CLEAR_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_EnableReceiveChannel()
383 SET_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_DisableReceiveChannel()
406 return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C1_IPCC_IsEnabledReceiveChannel()
Dstm32wlxx_hal_ipcc.h187 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
188 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
215 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
216 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_ipcc.h291 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_EnableTransmitChannel()
314 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); in LL_C1_IPCC_DisableTransmitChannel()
337 …return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)… in LL_C1_IPCC_IsEnabledTransmitChannel()
360 CLEAR_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_EnableReceiveChannel()
383 SET_BIT(IPCCx->C1MR, Channel); in LL_C1_IPCC_DisableReceiveChannel()
406 return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL); in LL_C1_IPCC_IsEnabledReceiveChannel()
Dstm32mp1xx_hal_ipcc.h186 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
187 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
214 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
215 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
/hal_stm32-latest/lib/stm32wb/hci/
Dhw_ipcc.c27 …nnel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) && (((~(IPCC->C1MR)) & (channel << 16U…
28 …( channel ) (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)…
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h653 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb1mxx.h669 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb30xx.h652 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb35xx.h761 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb55xx.h799 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb5mxx.h799 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h659 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wb15xx.h669 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h566 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wl54xx.h566 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32wl55xx.h566 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h2427 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151fxx_cm4.h2441 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151axx_ca7.h2427 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151axx_cm4.h2393 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151dxx_cm4.h2393 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151cxx_ca7.h2475 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member
Dstm32mp151cxx_cm4.h2441 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, … member

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