Home
last modified time | relevance | path

Searched refs:APB1ENR2 (Results 1 – 25 of 93) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h1075 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1077 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1123 … SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1125 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1131 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1133 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1139 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
1141 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
1147 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
1149 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
[all …]
Dstm32l5xx_ll_bus.h917 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
919 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
998 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1078 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h1591 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1593 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1599 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1601 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1608 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \
1610 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \
1618 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \
1620 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \
1627 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
1629 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
[all …]
Dstm32u5xx_ll_bus.h1898 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1900 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1969 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
2048 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h1236 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1238 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1319 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1321 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1328 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
1330 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
1337 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1339 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1403 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
1432 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
[all …]
Dstm32l4xx_ll_bus.h1114 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1116 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1201 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1285 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h1003 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1005 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1012 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1014 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1021 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
1023 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
1079 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
1082 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
1085 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
1452 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != …
[all …]
Dstm32g4xx_ll_bus.h938 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
940 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1015 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1089 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_bus.h1040 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1042 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1083 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1121 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
Dstm32wbaxx_hal_rcc.h893 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
895 … tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
911 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
1154 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0…
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_bus.h1803 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1805 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1824 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1U : 0U); in LL_APB1_GRP2_IsEnabledClock()
1842 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
Dstm32h7rsxx_hal_rcc.h1543 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN);\
1551 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN);\
1559 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN);\
1567 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN);\
1621 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN)
1623 #define __HAL_RCC_MDIOS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN)
1625 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN)
1627 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
2127 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) != 0U)
2129 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) != 0U)
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h961 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
963 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
1010 return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1055 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h938 SET_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
940 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_EnableClock()
989 return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
1036 CLEAR_BIT(RCC->APB1ENR2, Periphs); in LL_APB1_GRP2_DisableClock()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h2744 tmpreg = READ_REG(RCC->APB1ENR2); in LL_APB1_GRP2_EnableClock()
2761 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h544 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wle5xx.h544 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wl5mxx.h685 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wl54xx.h685 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h583 …__IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h416 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wb1mxx.h411 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wb30xx.h415 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h401 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member
Dstm32wb15xx.h411 …__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, … member

1234