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Searched refs:AHB5ENR (Results 1 – 18 of 18) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h1219 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN);\
1221 tmpreg = READ_REG(RCC->AHB5ENR);\
1227 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN);\
1229 tmpreg = READ_REG(RCC->AHB5ENR);\
1236 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN);\
1238 tmpreg = READ_REG(RCC->AHB5ENR);\
1245 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN);\
1247 tmpreg = READ_REG(RCC->AHB5ENR);\
1253 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN);\
1255 tmpreg = READ_REG(RCC->AHB5ENR);\
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Dstm32h7rsxx_ll_bus.h1131 SET_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_EnableClock()
1133 tmpreg = READ_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_EnableClock()
1166 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB5_GRP1_IsEnabledClock()
1198 CLEAR_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_bus.h861 SET_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_EnableClock()
863 tmpreg = READ_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_EnableClock()
881 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB5_GRP1_IsEnabledClock()
898 CLEAR_BIT(RCC->AHB5ENR, Periphs); in LL_AHB5_GRP1_DisableClock()
Dstm32wbaxx_hal_rcc.h804 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \
806 … tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \
813 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \
815 … tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \
820 #define __HAL_RCC_RADIO_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN)
823 #define __HAL_RCC_PTACONV_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN)
1128 #define __HAL_RCC_RADIO_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN) != 0U)
1130 #define __HAL_RCC_PTACONV_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) != 0U)
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h1760 tmpreg = READ_REG(RCC->AHB5ENR); in LL_AHB5_GRP1_EnableClock()
1827 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB5_GRP1_IsEnabledClock()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h581 …__IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address … member
Dstm32wba52xx.h674 …__IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address … member
Dstm32wba54xx.h701 …__IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address … member
Dstm32wba5mxx.h701 …__IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address … member
Dstm32wba55xx.h701 …__IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address … member
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h1469 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, … member
Dstm32h7s7xx.h1631 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, … member
Dstm32h7s3xx.h1562 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, … member
Dstm32h7r7xx.h1536 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, … member
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h2008 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register … member
Dstm32n657xx.h2134 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register … member
Dstm32n655xx.h2106 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register … member
Dstm32n647xx.h2036 …__IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register … member