Lines Matching refs:AHB5ENR

1219                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN);\
1221                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1227                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN);\
1229                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1236                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN);\
1238                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1245                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN);\
1247                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1253                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN);\
1255                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1261                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN);\
1263                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1269                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN);\
1271                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1277                                           SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN);\
1279                                           tmpreg = READ_REG(RCC->AHB5ENR);\
1286                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN);\
1288                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1296                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN);\
1298                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1303 #define __HAL_RCC_HPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN)
1305 #define __HAL_RCC_DMA2D_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN)
1308 #define __HAL_RCC_JPEG_CLK_DISABLE()   CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN)
1311 #define __HAL_RCC_FMC_CLK_DISABLE()    CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN)
1313 #define __HAL_RCC_XSPI1_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN)
1315 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN)
1317 #define __HAL_RCC_XSPI2_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN)
1319 #define __HAL_RCC_XSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN)
1322 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN)
1326 #define __HAL_RCC_GPU2D_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN)
2039 #define __HAL_RCC_HPDMA1_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) != 0U)
2041 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) != 0U)
2044 #define __HAL_RCC_JPEG_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) != 0U)
2047 #define __HAL_RCC_FMC_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) != 0U)
2049 #define __HAL_RCC_XSPI1_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) != 0U)
2051 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) != 0U)
2053 #define __HAL_RCC_XSPI2_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) != 0U)
2055 #define __HAL_RCC_XSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) != 0U)
2058 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) != 0U)
2062 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) != 0U)