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Searched refs:AHB3ENR (Results 1 – 25 of 155) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h767 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
769 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
777 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
784 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
786 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
795 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
804 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
[all …]
Dstm32h7xx_ll_bus.h569 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
571 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
618 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB3_GRP1_IsEnabledClock()
664 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
3368 SET_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_EnableClock()
3370 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_EnableClock()
3407 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB3_GRP1_IsEnabledClock()
3443 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_DisableClock()
5207 SET_BIT(RCC_C2->AHB3ENR, Periphs); in LL_C2_AHB3_GRP1_EnableClock()
5209 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); in LL_C2_AHB3_GRP1_EnableClock()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h1366 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
1368 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
1374 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
1376 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
1382 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
1384 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
1390 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
1392 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
1398 … SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
1400 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
[all …]
Dstm32u5xx_ll_bus.h1369 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
1371 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
1399 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
1436 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c366 RCC->AHB3ENR |= 0x00000001; in SystemInit_ExtMemCtl()
368 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
569 RCC->AHB3ENR |= 0x00000001; in SystemInit_ExtMemCtl()
571 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
703 RCC->AHB3ENR |= 0x00000001; in SystemInit_ExtMemCtl()
707 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
715 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
724 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32f401xc.h350 …__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Add… member
Dstm32f401xe.h350 …__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Add… member
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
1002 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
1010 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
1012 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
1020 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
1022 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
1030 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
1032 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
1038 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
1042 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
[all …]
Dstm32l4xx_ll_bus.h888 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
890 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
911 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
931 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1269 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1271 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1274 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1278 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1280 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1283 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1297 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1298 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1300 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1301 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
[all …]
Dstm32f4xx_ll_bus.h987 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
989 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
1008 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); in LL_AHB3_GRP1_IsEnabledClock()
1026 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_bus.h737 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
739 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
752 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); in LL_AHB3_GRP1_IsEnabledClock()
764 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
Dstm32f2xx_hal_rcc.h624 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
626 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
629 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
641 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
642 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_bus.h886 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
888 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
905 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); in LL_AHB3_GRP1_IsEnabledClock()
921 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
Dstm32f7xx_hal_rcc_ex.h895 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
897 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
903 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
905 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
909 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
910 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1572 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1573 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1575 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1576 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h992 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN);\
994 tmpreg = READ_REG(RCC->AHB3ENR);\
1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN);\
1002 tmpreg = READ_REG(RCC->AHB3ENR);\
1009 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN);\
1011 tmpreg = READ_REG(RCC->AHB3ENR);\
1019 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN);\
1021 tmpreg = READ_REG(RCC->AHB3ENR);\
1029 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN);\
1031 tmpreg = READ_REG(RCC->AHB3ENR);\
[all …]
Dstm32h7rsxx_ll_bus.h671 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
673 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
696 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB3_GRP1_IsEnabledClock()
718 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_bus.h728 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
730 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
745 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
760 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
Dstm32l5xx_hal_rcc.h907 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
909 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
915 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
917 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
921 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
923 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)
1479 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1481 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_bus.h746 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
748 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
765 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
781 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
Dstm32g4xx_hal_rcc.h780 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
782 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
790 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
792 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
798 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
802 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
1373 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1377 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
1381 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
1385 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h747 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
749 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
775 return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
800 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h637 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
639 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
681 return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
722 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dsystem_stm32f2xx.c322 RCC->AHB3ENR |= 0x00000001; in SystemInit_ExtMemCtl()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h1170 tmpreg = READ_REG(RCC->AHB3ENR); in LL_AHB3_GRP1_EnableClock()
1199 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()

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