Lines Matching refs:AHB3ENR

1366                                                     SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
1368 …                                          tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \
1374                                                     SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
1376 …                                              tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \
1382                                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
1384 …                                             tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \
1390                                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
1392 …                                             tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \
1398 …                                                     SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
1400 …                                           tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \
1406                                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
1408 …                                             tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \
1414                                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
1416 …                                            tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \
1422                                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
1424 …                                            tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \
1428 #define __HAL_RCC_LPGPIO1_CLK_DISABLE()         CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN)
1430 #define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN)
1432 #define __HAL_RCC_ADC4_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN)
1434 #define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN)
1436 #define __HAL_RCC_LPDMA1_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN)
1438 #define __HAL_RCC_ADF1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN)
1440 #define __HAL_RCC_GTZC2_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN)
1442 #define __HAL_RCC_SRAM4_CLK_DISABLE()          CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN)
2302 #define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) !…
2304 #define __HAL_RCC_PWR_IS_CLK_ENABLED()            (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U)
2306 #define __HAL_RCC_ADC4_IS_CLK_ENABLED()           (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U)
2308 #define __HAL_RCC_DAC1_IS_CLK_ENABLED()           (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U)
2310 #define __HAL_RCC_LPDMA1_IS_CLK_ENABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) !=…
2312 #define __HAL_RCC_ADF1_IS_CLK_ENABLED()           (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U)
2314 #define __HAL_RCC_GTZC2_IS_CLK_ENABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0…
2316 #define __HAL_RCC_SRAM4_IS_CLK_ENABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0…
2318 #define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) =…
2320 #define __HAL_RCC_PWR_IS_CLK_DISABLED()           (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U)
2322 #define __HAL_RCC_ADC4_IS_CLK_DISABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U)
2324 #define __HAL_RCC_DAC1_IS_CLK_DISABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U)
2326 #define __HAL_RCC_LPDMA1_IS_CLK_DISABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) ==…
2328 #define __HAL_RCC_ADF1_IS_CLK_DISABLED()          (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U)
2330 #define __HAL_RCC_GTZC2_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U)
2332 #define __HAL_RCC_SRAM4_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U)