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Searched refs:AHB2ENR (Results 1 – 25 of 163) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h600 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
602 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
608 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
610 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
616 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
618 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
624 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
626 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
632 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
634 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
[all …]
Dstm32g4xx_ll_bus.h454 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
456 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
499 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
541 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
746 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
754 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
762 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
769 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
771 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
779 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
781 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
[all …]
Dstm32l4xx_ll_bus.h566 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
568 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
615 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
661 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc.h902 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
904 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
910 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
912 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
918 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
920 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
926 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
928 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
935 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
937 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
[all …]
Dstm32h5xx_ll_bus.h892 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
894 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
946 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
997 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h736 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
738 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
746 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
754 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
762 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
768 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
770 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
[all …]
Dstm32l5xx_ll_bus.h436 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
438 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
481 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
524 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc.h652 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
654 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
660 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
662 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
668 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
670 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
678 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
680 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
687 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
689 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
[all …]
Dstm32wbaxx_ll_bus.h465 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
467 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
503 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
538 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc_ex.h211 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
213 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
217 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
223 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
225 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
230 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
232 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
236 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
237 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
251 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
[all …]
Dstm32f2xx_ll_bus.h575 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
577 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
600 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); in LL_AHB2_GRP1_IsEnabledClock()
622 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
Dstm32f2xx_hal_rcc.h582 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
587 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
589 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
593 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
594 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
606 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
607 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
609 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
610 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h1152 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1154 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1162 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1164 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1172 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1174 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1182 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1184 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1191 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1193 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
[all …]
Dstm32h7xx_ll_bus.h1127 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
1129 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
1166 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB2_GRP1_IsEnabledClock()
1202 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
3774 SET_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_EnableClock()
3776 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_EnableClock()
3809 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB2_GRP1_IsEnabledClock()
3841 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_DisableClock()
5557 SET_BIT(RCC_C2->AHB2ENR, Periphs); in LL_C2_AHB2_GRP1_EnableClock()
5559 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); in LL_C2_AHB2_GRP1_EnableClock()
[all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1188 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1190 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1193 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
1198 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1200 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1205 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1207 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1211 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
1212 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
1215 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
[all …]
Dstm32f4xx_ll_bus.h805 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
807 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
832 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); in LL_AHB2_GRP1_IsEnabledClock()
856 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h816 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
818 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
821 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
827 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
829 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
832 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
837 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
839 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
845 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
847 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
[all …]
Dstm32f7xx_ll_bus.h696 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
698 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
725 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); in LL_AHB2_GRP1_IsEnabledClock()
751 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dsystem_stm32h7xx.c270 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); in SystemInit()
272 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); in SystemInit()
274 RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); in SystemInit()
277 tmpreg = RCC->AHB2ENR; in SystemInit()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dsystem_stm32h7xx_singlecore.c260 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); in SystemInit()
262 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); in SystemInit()
264 RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); in SystemInit()
267 tmpreg = RCC->AHB2ENR; in SystemInit()
Dsystem_stm32h7xx.c275 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); in SystemInit()
277 RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); in SystemInit()
279 RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); in SystemInit()
282 tmpreg = RCC->AHB2ENR; in SystemInit()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h930 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN);\
932 tmpreg = READ_REG(RCC->AHB2ENR);\
938 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
940 tmpreg = READ_REG(RCC->AHB2ENR);\
946 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
948 tmpreg = READ_REG(RCC->AHB2ENR);\
954 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN);\
956 tmpreg = READ_REG(RCC->AHB2ENR);\
962 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN);\
964 tmpreg = READ_REG(RCC->AHB2ENR);\
[all …]
Dstm32h7rsxx_ll_bus.h521 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
523 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
544 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB2_GRP1_IsEnabledClock()
564 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h542 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
544 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
572 return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
599 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()

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