Lines Matching refs:AHB2ENR

930                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN);\
932                                             tmpreg = READ_REG(RCC->AHB2ENR);\
938                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
940                                             tmpreg = READ_REG(RCC->AHB2ENR);\
946                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
948                                             tmpreg = READ_REG(RCC->AHB2ENR);\
954                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN);\
956                                             tmpreg = READ_REG(RCC->AHB2ENR);\
962                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN);\
964                                             tmpreg = READ_REG(RCC->AHB2ENR);\
968 #define __HAL_RCC_PSSI_CLK_DISABLE()   CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN)
970 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN)
972 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN)
974 #define __HAL_RCC_SRAM1_CLK_DISABLE()  CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN)
976 #define __HAL_RCC_SRAM2_CLK_DISABLE()  CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN)
1949 #define __HAL_RCC_PSSI_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) != 0U)
1951 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U)
1953 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) != 0U)
1955 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) != 0U)
1957 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U)