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Searched refs:ADC_CFGR1_AWDCH_4 (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_adc.h466 #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
468 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH…
469 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH…
Dstm32l0xx_ll_adc.h111 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 …
112 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 …
113 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 …
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_adc.h111 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 …
112 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 …
113 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 …
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h694 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f030x8.h710 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f070x6.h739 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f031x6.h704 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f030xc.h726 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f038xx.h703 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f070xb.h762 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f058xx.h809 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
Dstm32f051x8.h810 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h719 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l010x8.h677 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l010xb.h682 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l011xx.h689 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l021xx.h710 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l031xx.h698 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l051xx.h733 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l010x4.h669 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l010x6.h675 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l081xx.h776 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l071xx.h755 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l052xx.h842 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro
Dstm32l062xx.h863 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ macro

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