Searched refs:ADC_CFGR1_AWDCH_3 (Results 1 – 25 of 38) sorted by relevance
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457 #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)458 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_…459 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…460 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…461 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…462 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…463 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…464 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH…
103 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 …104 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 …105 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 …106 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 …107 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH…108 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH…109 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH…110 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH…
693 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
709 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
738 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
703 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
725 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
702 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
761 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
808 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
809 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) macro
718 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
676 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
681 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
688 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
709 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
697 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
732 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
668 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
674 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
775 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
754 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
841 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
862 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ macro
