Home
last modified time | relevance | path

Searched refs:Timing (Results 1 – 25 of 210) sorted by relevance

123456789

/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c399 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
407 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
408 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
409 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
410 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
411 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
412 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
413 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
418 … ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
Dstm32f4xx_ll_fsmc.c380 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
388 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
389 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
390 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
391 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
392 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
393 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
394 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
399 … ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c329 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
334 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
335 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
336 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
337 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
338 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
339 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
340 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
344 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
345 … ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c313 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
318 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
319 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
320 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
321 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
322 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
323 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
324 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
328 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
329 … ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c327 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
333 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
334 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
335 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
336 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
338 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
339 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
344 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
345 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c330 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
336 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
338 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
339 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
340 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
341 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
342 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
347 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
348 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c386 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
392 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
393 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
394 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
395 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
396 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
397 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
398 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
399 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
404 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c325 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
332 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
333 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
334 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
335 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
336 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
342 … ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c325 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
332 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
333 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
334 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
335 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
336 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
342 … ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c400 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
406 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
407 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
409 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
411 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
412 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
413 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
414 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
415 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
420 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c362 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
368 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
369 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
370 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
371 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
372 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
373 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
374 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
375 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
380 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c367 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
373 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
374 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
375 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
376 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
377 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
378 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
379 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
380 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
384 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c367 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
373 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
374 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
375 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
376 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
377 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
378 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
379 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
380 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
385 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c335 …_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
341 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
342 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
343 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
344 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
345 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
346 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
347 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
348 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
352 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c276 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
281 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
282 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
283 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
284 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
285 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
286 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
287 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
291 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
292 … ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_dsi.h1209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S…
1350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ argument
1351 ((Timing) == DSI_TLPX_CLK ) || \
1352 ((Timing) == DSI_THS_EXIT ) || \
1353 ((Timing) == DSI_TLPX_DATA ) || \
1354 ((Timing) == DSI_THS_ZERO ) || \
1355 ((Timing) == DSI_THS_TRAIL ) || \
1356 ((Timing) == DSI_THS_PREPARE ) || \
1357 ((Timing) == DSI_TCLK_ZERO ) || \
1358 ((Timing) == DSI_TCLK_PREPARE))
Dstm32f4xx_ll_fmc.h1288 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1290 … FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1320 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1322 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1352 FMC_NAND_PCC_TimingTypeDef *Timing);
1354 … FMC_NAND_PCC_TimingTypeDef *Timing);
1356 FMC_NAND_PCC_TimingTypeDef *Timing);
1375 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
Dstm32f4xx_ll_fsmc.h991 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
993 … FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1023 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1025 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1055 FSMC_NAND_PCC_TimingTypeDef *Timing);
1057 … FSMC_NAND_PCC_TimingTypeDef *Timing);
1059 FSMC_NAND_PCC_TimingTypeDef *Timing);
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_dsi.h1209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S…
1350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ argument
1351 ((Timing) == DSI_TLPX_CLK ) || \
1352 ((Timing) == DSI_THS_EXIT ) || \
1353 ((Timing) == DSI_TLPX_DATA ) || \
1354 ((Timing) == DSI_THS_ZERO ) || \
1355 ((Timing) == DSI_THS_TRAIL ) || \
1356 ((Timing) == DSI_THS_PREPARE ) || \
1357 ((Timing) == DSI_TCLK_ZERO ) || \
1358 ((Timing) == DSI_TCLK_PREPARE))
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_dsi.h1209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S…
1350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ argument
1351 ((Timing) == DSI_TLPX_CLK ) || \
1352 ((Timing) == DSI_THS_EXIT ) || \
1353 ((Timing) == DSI_TLPX_DATA ) || \
1354 ((Timing) == DSI_THS_ZERO ) || \
1355 ((Timing) == DSI_THS_TRAIL ) || \
1356 ((Timing) == DSI_THS_PREPARE ) || \
1357 ((Timing) == DSI_TCLK_ZERO ) || \
1358 ((Timing) == DSI_TCLK_PREPARE))
Dstm32h7xx_ll_fmc.h1061 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1063 … FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1091 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1093 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1122 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_dsi.h1209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S…
1350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ argument
1351 ((Timing) == DSI_TLPX_CLK ) || \
1352 ((Timing) == DSI_THS_EXIT ) || \
1353 ((Timing) == DSI_TLPX_DATA ) || \
1354 ((Timing) == DSI_THS_ZERO ) || \
1355 ((Timing) == DSI_THS_TRAIL ) || \
1356 ((Timing) == DSI_THS_PREPARE ) || \
1357 ((Timing) == DSI_TCLK_ZERO ) || \
1358 ((Timing) == DSI_TCLK_PREPARE))
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_fsmc.h800 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
802 … FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
830 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
832 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
860 FSMC_NAND_PCC_TimingTypeDef *Timing);
862 … FSMC_NAND_PCC_TimingTypeDef *Timing);
864 FSMC_NAND_PCC_TimingTypeDef *Timing);
/hal_stm32-3.7.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_fmc.h851 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
853 … FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
883 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
885 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
915 FMC_NAND_PCC_TimingTypeDef *Timing);
917 … FMC_NAND_PCC_TimingTypeDef *Timing);
919 FMC_NAND_PCC_TimingTypeDef *Timing);
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_fsmc.h867 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
869 … FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
899 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
901 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
931 FSMC_NAND_PCC_TimingTypeDef *Timing);
933 … FSMC_NAND_PCC_TimingTypeDef *Timing);
935 FSMC_NAND_PCC_TimingTypeDef *Timing);

123456789