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/hal_stm32-3.7.0/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_cortex.h300 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
301 ((STATE) == MPU_REGION_DISABLE))
303 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
304 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
306 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
307 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
309 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
310 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
312 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
313 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_cortex.h283 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
284 ((STATE) == MPU_REGION_DISABLE))
286 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
287 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
289 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
290 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
292 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
293 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
295 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
296 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_cortex.h302 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
303 ((STATE) == MPU_REGION_DISABLE))
305 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
306 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
308 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
309 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
311 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
312 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
314 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
315 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_cortex.h321 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
322 ((STATE) == MPU_REGION_DISABLE))
324 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
325 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
327 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
330 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
331 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
333 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
334 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
Dstm32f2xx_hal_dma.h707 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
708 ((STATE) == DMA_PINC_DISABLE))
710 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
711 ((STATE) == DMA_MINC_DISABLE))
730 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ argument
731 ((STATE) == DMA_FIFOMODE_ENABLE))
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_cortex.h321 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
322 ((STATE) == MPU_REGION_DISABLE))
324 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
325 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
327 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
330 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
331 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
333 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
334 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
Dstm32f4xx_hal_dma.h736 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
737 ((STATE) == DMA_PINC_DISABLE))
739 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
740 ((STATE) == DMA_MINC_DISABLE))
759 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ argument
760 ((STATE) == DMA_FIFOMODE_ENABLE))
/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_cortex.h294 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
295 ((STATE) == MPU_REGION_DISABLE))
297 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
298 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
300 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
301 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
303 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
304 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
306 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
307 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_cortex.h321 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
322 ((STATE) == MPU_REGION_DISABLE))
324 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
325 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
327 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
330 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
331 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
333 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
334 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
Dstm32f1xx_hal_dma.h414 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
415 ((STATE) == DMA_PINC_DISABLE))
417 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
418 ((STATE) == DMA_MINC_DISABLE))
/hal_stm32-3.7.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_cortex.h331 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
332 ((STATE) == MPU_REGION_DISABLE))
334 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
335 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
337 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
338 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
340 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
341 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
343 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
344 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_hal_cortex.h331 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
332 ((STATE) == MPU_REGION_DISABLE))
334 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
335 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
337 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
338 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
340 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
341 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
343 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
344 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_cortex.h309 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
310 ((STATE) == MPU_REGION_DISABLE))
312 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
313 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
315 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
316 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
318 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
319 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
321 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
322 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_cortex.h321 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
322 ((STATE) == MPU_REGION_DISABLE))
324 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
325 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
327 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
330 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
331 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
333 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
334 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
Dstm32f7xx_hal_dma.h681 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
682 ((STATE) == DMA_PINC_DISABLE))
684 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
685 ((STATE) == DMA_MINC_DISABLE))
704 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ argument
705 ((STATE) == DMA_FIFOMODE_ENABLE))
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_cortex.h332 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
333 ((STATE) == MPU_REGION_DISABLE))
335 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
336 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
338 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
339 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
341 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
342 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
344 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
345 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_cortex.h324 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
325 ((STATE) == MPU_REGION_DISABLE))
327 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
328 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
330 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
331 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
333 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
334 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
336 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
337 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_hal_cortex.h348 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
349 ((STATE) == MPU_REGION_DISABLE))
351 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
352 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
354 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
355 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
357 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
358 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
360 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
361 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_cortex.h357 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
358 ((STATE) == MPU_REGION_DISABLE))
360 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
361 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
363 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
364 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
366 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
367 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
369 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
370 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_cortex.h323 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
324 ((STATE) == MPU_REGION_DISABLE))
326 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
327 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
329 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ argument
330 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
331 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_cortex.h333 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
334 ((STATE) == MPU_REGION_DISABLE))
336 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
337 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
339 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ argument
340 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
341 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_cortex.h330 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
331 ((STATE) == MPU_REGION_DISABLE))
333 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
334 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
336 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ argument
337 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
338 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
Dstm32u5xx_hal_sai.h826 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ argument
827 ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
828 ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
830 #define IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE) argument
921 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ argument
922 ((STATE) == SAI_OUTPUT_RELEASED))
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_cortex.h348 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
349 ((STATE) == MPU_REGION_DISABLE))
351 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
352 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
354 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ argument
355 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
356 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
Dstm32h5xx_hal_flash_ex.h953 #define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) … argument
954 … ((STATE) == OB_PROD_STATE_PROVISIONING) || \
955 … ((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \
956 … ((STATE) == OB_PROD_STATE_TZ_CLOSED) || \
957 … ((STATE) == OB_PROD_STATE_CLOSED) || \
958 … ((STATE) == OB_PROD_STATE_LOCKED) || \
959 … ((STATE) == OB_PROD_STATE_REGRESSION) || \
960 ((STATE) == OB_PROD_STATE_NS_REGRESSION))

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