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Searched refs:SDCR (Results 1 – 25 of 56) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c370 FMC_Bank5_6->SDCR[0] = 0x000019E4; in SystemInit_ExtMemCtl()
417 tmpreg = FMC_Bank5_6->SDCR[0]; in SystemInit_ExtMemCtl()
418 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); in SystemInit_ExtMemCtl()
575 FMC_Bank5_6->SDCR[0] = 0x00001954; in SystemInit_ExtMemCtl()
577 FMC_Bank5_6->SDCR[0] = 0x000019E4; in SystemInit_ExtMemCtl()
637 tmpreg = FMC_Bank5_6->SDCR[0]; in SystemInit_ExtMemCtl()
638 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); in SystemInit_ExtMemCtl()
Dstm32f446xx.h447 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f427xx.h561 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f439xx.h564 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f437xx.h562 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f429xx.h563 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f479xx.h627 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f469xx.h626 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c822 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
836 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
844 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
925 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
966 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
983 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c807 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
821 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
829 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
910 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
951 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
968 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c807 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
821 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
829 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
910 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
951 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
968 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c877 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
891 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
899 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
980 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
1021 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
1038 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c1199 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1213 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1221 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
1302 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
1343 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
1360 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
/hal_stm32-3.7.0/stm32cube/stm32f7xx/soc/
Dstm32f722xx.h418 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f723xx.h418 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f733xx.h419 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f730xx.h419 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f732xx.h419 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f745xx.h565 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f746xx.h567 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f750xx.h568 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f756xx.h568 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f765xx.h609 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f767xx.h612 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member
Dstm32f777xx.h613 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ member

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