/hal_stm32-3.7.0/stm32cube/stm32l4xx/soc/ |
D | stm32l412xx.h | 6169 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6170 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l422xx.h | 6394 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6395 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l431xx.h | 10095 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 10096 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l432xx.h | 9699 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 9700 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l433xx.h | 10205 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 10206 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l451xx.h | 10372 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 10373 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l442xx.h | 9924 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 9925 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l452xx.h | 10450 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 10451 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32l471xx.h | 11385 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 11386 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb30xx.h | 6950 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6951 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb50xx.h | 6951 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6952 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb1mxx.h | 6641 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6642 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb35xx.h | 7907 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 7908 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb55xx.h | 8134 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8135 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb5mxx.h | 8134 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8135 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 6475 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6476 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32wb15xx.h | 6641 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 6642 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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/hal_stm32-3.7.0/stm32cube/stm32g4xx/soc/ |
D | stm32gbk1cb.h | 8059 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8060 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g431xx.h | 8087 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8088 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g441xx.h | 8317 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8318 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g4a1xx.h | 8719 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8720 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g491xx.h | 8489 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8490 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g471xx.h | 8656 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 8657 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g473xx.h | 9206 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 9207 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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D | stm32g483xx.h | 9436 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ macro 9437 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
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