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Searched refs:OR2 (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_tim_ex.c2186 tmporx = htim->Instance->OR2; in HAL_TIMEx_ConfigBreakInput()
2202 htim->Instance->OR2 = tmporx; in HAL_TIMEx_ConfigBreakInput()
2473 tmpor2 = htim->Instance->OR2; in HAL_TIMEx_RemapConfig()
2478 htim->Instance->OR2 = tmpor2; in HAL_TIMEx_RemapConfig()
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_tim_ex.c2182 tmporx = htim->Instance->OR2; in HAL_TIMEx_ConfigBreakInput()
2196 htim->Instance->OR2 = tmporx; in HAL_TIMEx_ConfigBreakInput()
2330 tmpor2 = htim->Instance->OR2; in HAL_TIMEx_RemapConfig()
2335 htim->Instance->OR2 = tmpor2; in HAL_TIMEx_RemapConfig()
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_tim.h3458 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); in LL_TIM_SetETRSource()
3773 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_EnableBreakInputSource()
3802 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_DisableBreakInputSource()
3832 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_SetBreakInputSourcePolarity()
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_tim.h3462 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); in LL_TIM_SetETRSource()
3720 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_EnableBreakInputSource()
3749 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_DisableBreakInputSource()
3779 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); in LL_TIM_SetBreakInputSourcePolarity()
/hal_stm32-3.7.0/stm32cube/stm32l4xx/soc/
Dstm32l412xx.h687 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l422xx.h688 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l431xx.h829 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l432xx.h796 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l433xx.h845 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l451xx.h849 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l442xx.h797 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l452xx.h850 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l471xx.h903 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l462xx.h851 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l443xx.h846 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l475xx.h904 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l485xx.h905 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l476xx.h919 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l486xx.h920 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l4r5xx.h1018 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l4s5xx.h1019 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l4r7xx.h1090 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l4s7xx.h1091 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
Dstm32l496xx.h992 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member
/hal_stm32-3.7.0/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h1093 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ member

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