Searched refs:FSMC_PATTx_ATTHIZx_Pos (Results 1 – 5 of 5) sorted by relevance
634 … ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()642 … ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()936 ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); in FSMC_PCCARD_AttributeSpace_Timing_Init()
5217 #define FSMC_PATTx_ATTHIZx_Pos (24U) macro5218 #define FSMC_PATTx_ATTHIZx_Msk (0xFFUL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */5220 #define FSMC_PATTx_ATTHIZx_0 (0x01UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */5221 #define FSMC_PATTx_ATTHIZx_1 (0x02UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */5222 #define FSMC_PATTx_ATTHIZx_2 (0x04UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */5223 #define FSMC_PATTx_ATTHIZx_3 (0x08UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */5224 #define FSMC_PATTx_ATTHIZx_4 (0x10UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */5225 #define FSMC_PATTx_ATTHIZx_5 (0x20UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */5226 #define FSMC_PATTx_ATTHIZx_6 (0x40UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */5227 #define FSMC_PATTx_ATTHIZx_7 (0x80UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
5292 #define FSMC_PATTx_ATTHIZx_Pos (24U) macro5293 #define FSMC_PATTx_ATTHIZx_Msk (0xFFUL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */5295 #define FSMC_PATTx_ATTHIZx_0 (0x01UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */5296 #define FSMC_PATTx_ATTHIZx_1 (0x02UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */5297 #define FSMC_PATTx_ATTHIZx_2 (0x04UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */5298 #define FSMC_PATTx_ATTHIZx_3 (0x08UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */5299 #define FSMC_PATTx_ATTHIZx_4 (0x10UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */5300 #define FSMC_PATTx_ATTHIZx_5 (0x20UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */5301 #define FSMC_PATTx_ATTHIZx_6 (0x40UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */5302 #define FSMC_PATTx_ATTHIZx_7 (0x80UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
5515 #define FSMC_PATTx_ATTHIZx_Pos (24U) macro5516 #define FSMC_PATTx_ATTHIZx_Msk (0xFFUL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */5518 #define FSMC_PATTx_ATTHIZx_0 (0x01UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */5519 #define FSMC_PATTx_ATTHIZx_1 (0x02UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */5520 #define FSMC_PATTx_ATTHIZx_2 (0x04UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */5521 #define FSMC_PATTx_ATTHIZx_3 (0x08UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */5522 #define FSMC_PATTx_ATTHIZx_4 (0x10UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */5523 #define FSMC_PATTx_ATTHIZx_5 (0x20UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */5524 #define FSMC_PATTx_ATTHIZx_6 (0x40UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */5525 #define FSMC_PATTx_ATTHIZx_7 (0x80UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
5445 #define FSMC_PATTx_ATTHIZx_Pos (24U) macro5446 #define FSMC_PATTx_ATTHIZx_Msk (0xFFUL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */5448 #define FSMC_PATTx_ATTHIZx_0 (0x01UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */5449 #define FSMC_PATTx_ATTHIZx_1 (0x02UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */5450 #define FSMC_PATTx_ATTHIZx_2 (0x04UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */5451 #define FSMC_PATTx_ATTHIZx_3 (0x08UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */5452 #define FSMC_PATTx_ATTHIZx_4 (0x10UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */5453 #define FSMC_PATTx_ATTHIZx_5 (0x20UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */5454 #define FSMC_PATTx_ATTHIZx_6 (0x40UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */5455 #define FSMC_PATTx_ATTHIZx_7 (0x80UL << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
