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Searched refs:FSMC_BTRx_ADDHLD_Pos (Results 1 – 10 of 10) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c292 … ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
/hal_stm32-3.7.0/stm32cube/stm32f1xx/soc/
Dstm32f101xe.h4971 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
4972 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
4974 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
4975 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
4976 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
4977 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f101xg.h5046 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
5047 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5049 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
5050 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
5051 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
5052 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f100xe.h5179 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
5180 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5182 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
5183 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
5184 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
5185 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f103xg.h5269 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
5270 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5272 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
5273 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
5274 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
5275 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32f103xe.h5199 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
5200 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5202 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
5203 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
5204 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
5205 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c345 … ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
/hal_stm32-3.7.0/stm32cube/stm32l1xx/soc/
Dstm32l151xd.h3370 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
3371 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
3373 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
3374 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
3375 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
3376 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32l152xd.h3387 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
3388 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
3390 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
3391 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
3392 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
3393 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
Dstm32l162xd.h3517 #define FSMC_BTRx_ADDHLD_Pos (4U) macro
3518 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
3520 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
3521 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
3522 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
3523 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */