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Searched refs:BTCR (Results 1 – 25 of 172) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c194 MODIFY_REG(Device->BTCR[Init->NSBank], in FMC_NORSRAM_Init()
230 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
290 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
298 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
352 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
362 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
364 …tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTR1_CLKDIV_Pos… in FMC_NORSRAM_Timing_Init()
366 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
455 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c282 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
287 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
294 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
355 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
360 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
363 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
420 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
429 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
439 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
441 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c250 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
255 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
261 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
319 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
324 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
327 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
379 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
390 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
392 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
394 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c255 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
260 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
266 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
324 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
329 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
332 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
384 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
394 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
396 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
398 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c255 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
260 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
266 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
324 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
329 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
332 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
384 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
395 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
397 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
399 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c422 FMC_Bank1->BTCR[2] = 0x00001011; in SystemInit_ExtMemCtl()
423 FMC_Bank1->BTCR[3] = 0x00000201; in SystemInit_ExtMemCtl()
428 FMC_Bank1->BTCR[2] = 0x00001091; in SystemInit_ExtMemCtl()
429 FMC_Bank1->BTCR[3] = 0x00110212; in SystemInit_ExtMemCtl()
709 FMC_Bank1->BTCR[2] = 0x00001011; in SystemInit_ExtMemCtl()
710 FMC_Bank1->BTCR[3] = 0x00000201; in SystemInit_ExtMemCtl()
717 FMC_Bank1->BTCR[2] = 0x00001091; in SystemInit_ExtMemCtl()
718 FMC_Bank1->BTCR[3] = 0x00110212; in SystemInit_ExtMemCtl()
726 FSMC_Bank1->BTCR[2] = 0x00001011; in SystemInit_ExtMemCtl()
727 FSMC_Bank1->BTCR[3] = 0x00000201; in SystemInit_ExtMemCtl()
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fsmc.c314 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
320 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock); in FSMC_NORSRAM_Init()
328 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FSMC_NORSRAM_Init()
357 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
362 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
365 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
408 if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) in FSMC_NORSRAM_Timing_Init()
410 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos)); in FSMC_NORSRAM_Timing_Init()
412 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr); in FSMC_NORSRAM_Timing_Init()
[all …]
Dstm32f4xx_ll_fmc.c333 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
376 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
381 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
384 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
427 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
429 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
431 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c268 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
273 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
279 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
307 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
312 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
315 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
346 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
356 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
358 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
360 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c263 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
268 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
274 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
302 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
307 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
310 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
350 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
352 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
354 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c263 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
268 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
274 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
302 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
307 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
310 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
350 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
352 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
354 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c271 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
276 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
304 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
309 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
312 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
343 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
353 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
355 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
357 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
438 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c274 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
279 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
285 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
343 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
348 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
351 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
403 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
414 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
416 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
418 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c225 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
253 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
258 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
261 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
291 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
379 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Enable()
397 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Disable()
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c278 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
306 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
311 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
314 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
344 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
446 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Enable()
464 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Disable()
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
290 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
298 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
328 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
416 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Enable()
434 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Disable()
/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_fmc.h446 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
452 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
464 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1…
472 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR…
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_fmc.h653 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
659 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
667 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
676 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_fmc.h870 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
876 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
888 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
897 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_fmc.h870 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
876 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
888 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
897 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_fmc.h942 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
948 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
961 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
970 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
/hal_stm32-3.7.0/stm32cube/stm32f2xx/soc/
Dsystem_stm32f2xx.c325 FSMC_Bank1->BTCR[2] = 0x00001011; in SystemInit_ExtMemCtl()
326 FSMC_Bank1->BTCR[3] = 0x00000201; in SystemInit_ExtMemCtl()
/hal_stm32-3.7.0/stm32cube/stm32f1xx/soc/
Dsystem_stm32f1xx.c390 FSMC_Bank1->BTCR[4U] = 0x00001091U; in SystemInit_ExtMemCtl()
391 FSMC_Bank1->BTCR[5U] = 0x00110212U; in SystemInit_ExtMemCtl()
/hal_stm32-3.7.0/stm32cube/stm32l1xx/soc/
Dsystem_stm32l1xx.c375 FSMC_Bank1->BTCR[4] = 0x00001011; in SystemInit_ExtMemCtl()
376 FSMC_Bank1->BTCR[5] = 0x00000300; in SystemInit_ExtMemCtl()
/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_fsmc.h445 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
454 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\

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