/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/ |
D | stm32f051x8.h | 5685 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 5686 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f058xx.h | 5654 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 5655 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f071xb.h | 6238 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6239 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f042x6.h | 9460 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 9461 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f048xx.h | 9424 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 9425 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f072xb.h | 10035 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10036 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f078xx.h | 10005 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10006 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f098xx.h | 10659 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10660 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f091xc.h | 10692 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10693 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6211 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6212 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l053xx.h | 6370 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6371 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l062xx.h | 6348 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6349 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l063xx.h | 6505 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6506 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l072xx.h | 6507 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6508 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l073xx.h | 6666 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6667 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l082xx.h | 6644 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6645 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32l083xx.h | 6803 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 6804 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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/hal_stm32-3.6.0/stm32cube/stm32f3xx/soc/ |
D | stm32f318xx.h | 7459 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 7460 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f301x8.h | 7472 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 7473 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f373xc.h | 10646 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10647 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f378xx.h | 10544 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 10545 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32f302xc.h | 11385 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 11386 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb15xx.h | 8125 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 8126 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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D | stm32wb10xx.h | 7953 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 7954 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8125 #define TSC_IOASCR_G7_IO4_Pos (27U) macro 8126 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
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