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Searched refs:SPI_CR1_CRCL_Msk (Results 1 – 25 of 108) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/
Dstm32f070x6.h3867 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
3868 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f030x6.h3787 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
3788 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f030x8.h3831 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
3832 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f070xb.h4025 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4026 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f030xc.h4157 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4158 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f031x6.h3942 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
3943 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f038xx.h3914 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
3915 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f051x8.h4442 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4443 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f058xx.h4414 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4415 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f071xb.h4952 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4953 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
/hal_stm32-3.6.0/stm32cube/stm32c0xx/soc/
Dstm32c031xx.h4989 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4990 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32c011xx.h4829 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
4830 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
/hal_stm32-3.6.0/stm32cube/stm32g0xx/soc/
Dstm32g070xx.h5538 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5539 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g050xx.h5386 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5387 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g030xx.h5340 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5341 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g051xx.h5961 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5962 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g031xx.h5586 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5587 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g041xx.h5884 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
5885 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g061xx.h6259 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6260 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g071xx.h6349 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6350 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g0b0xx.h6654 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6655 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32g081xx.h6647 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6648 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
/hal_stm32-3.6.0/stm32cube/stm32f3xx/soc/
Dstm32f318xx.h6063 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6064 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Dstm32f301x8.h6073 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
6074 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
/hal_stm32-3.6.0/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h7368 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ macro
7369 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */

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