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Searched refs:SPI_CR1_CPHA_Msk (Results 1 – 25 of 190) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4309 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4310 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f101xb.h4371 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4372 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f100xb.h4776 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4777 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f102x6.h5428 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
5429 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f100xe.h5290 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
5291 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/
Dstm32f070x6.h3837 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3838 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f030x6.h3757 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3758 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f030x8.h3801 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3802 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f070xb.h3995 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3996 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f030xc.h4127 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4128 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f031x6.h3912 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3913 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f038xx.h3884 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
3885 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f051x8.h4412 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4413 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32f058xx.h4384 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4385 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/
Dstm32l051xx.h4648 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4649 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l010x4.h4307 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4308 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l011xx.h4416 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4417 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l021xx.h4553 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4554 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l031xx.h4539 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4540 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l041xx.h4676 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4677 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l010x6.h4359 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4360 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l010x8.h4351 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4352 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l010xb.h4399 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4400 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l071xx.h4782 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4783 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Dstm32l081xx.h4919 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ macro
4920 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */

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