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Searched refs:DMA_ISR_GIF5_Pos (Results 1 – 25 of 147) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h2879 #define DMA_ISR_GIF5_Pos (16U) macro
2880 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f101xb.h2941 #define DMA_ISR_GIF5_Pos (16U) macro
2942 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f100xb.h3093 #define DMA_ISR_GIF5_Pos (16U) macro
3094 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f102x6.h2928 #define DMA_ISR_GIF5_Pos (16U) macro
2929 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f100xe.h3440 #define DMA_ISR_GIF5_Pos (16U) macro
3441 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/
Dstm32f070x6.h1053 #define DMA_ISR_GIF5_Pos (16U) macro
1054 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f030x6.h1008 #define DMA_ISR_GIF5_Pos (16U) macro
1009 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f030x8.h1030 #define DMA_ISR_GIF5_Pos (16U) macro
1031 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f070xb.h1085 #define DMA_ISR_GIF5_Pos (16U) macro
1086 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f030xc.h1049 #define DMA_ISR_GIF5_Pos (16U) macro
1050 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f031x6.h1024 #define DMA_ISR_GIF5_Pos (16U) macro
1025 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f038xx.h1023 #define DMA_ISR_GIF5_Pos (16U) macro
1024 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f051x8.h1465 #define DMA_ISR_GIF5_Pos (16U) macro
1466 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32f058xx.h1464 #define DMA_ISR_GIF5_Pos (16U) macro
1465 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/
Dstm32l051xx.h1179 #define DMA_ISR_GIF5_Pos (16U) macro
1180 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l010x4.h1021 #define DMA_ISR_GIF5_Pos (16U) macro
1022 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l011xx.h1126 #define DMA_ISR_GIF5_Pos (16U) macro
1127 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l021xx.h1254 #define DMA_ISR_GIF5_Pos (16U) macro
1255 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l031xx.h1138 #define DMA_ISR_GIF5_Pos (16U) macro
1139 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l041xx.h1266 #define DMA_ISR_GIF5_Pos (16U) macro
1267 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l010x6.h1027 #define DMA_ISR_GIF5_Pos (16U) macro
1028 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l010x8.h1029 #define DMA_ISR_GIF5_Pos (16U) macro
1030 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l010xb.h1037 #define DMA_ISR_GIF5_Pos (16U) macro
1038 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l071xx.h1210 #define DMA_ISR_GIF5_Pos (16U) macro
1211 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Dstm32l081xx.h1338 #define DMA_ISR_GIF5_Pos (16U) macro
1339 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */

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