Searched refs:DMA_IFCR_CHTIF1_Pos (Results 1 – 25 of 149) sorted by relevance
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2923 #define DMA_IFCR_CHTIF1_Pos (2U) macro2924 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
2985 #define DMA_IFCR_CHTIF1_Pos (2U) macro2986 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3137 #define DMA_IFCR_CHTIF1_Pos (2U) macro3138 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
2972 #define DMA_IFCR_CHTIF1_Pos (2U) macro2973 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3484 #define DMA_IFCR_CHTIF1_Pos (2U) macro3485 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1073 #define DMA_IFCR_CHTIF1_Pos (2U) macro1074 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1028 #define DMA_IFCR_CHTIF1_Pos (2U) macro1029 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1050 #define DMA_IFCR_CHTIF1_Pos (2U) macro1051 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1105 #define DMA_IFCR_CHTIF1_Pos (2U) macro1106 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1069 #define DMA_IFCR_CHTIF1_Pos (2U) macro1070 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1044 #define DMA_IFCR_CHTIF1_Pos (2U) macro1045 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1043 #define DMA_IFCR_CHTIF1_Pos (2U) macro1044 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1485 #define DMA_IFCR_CHTIF1_Pos (2U) macro1486 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1484 #define DMA_IFCR_CHTIF1_Pos (2U) macro1485 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1223 #define DMA_IFCR_CHTIF1_Pos (2U) macro1224 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1065 #define DMA_IFCR_CHTIF1_Pos (2U) macro1066 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1146 #define DMA_IFCR_CHTIF1_Pos (2U) macro1147 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1274 #define DMA_IFCR_CHTIF1_Pos (2U) macro1275 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1182 #define DMA_IFCR_CHTIF1_Pos (2U) macro1183 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1310 #define DMA_IFCR_CHTIF1_Pos (2U) macro1311 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1071 #define DMA_IFCR_CHTIF1_Pos (2U) macro1072 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1081 #define DMA_IFCR_CHTIF1_Pos (2U) macro1082 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1254 #define DMA_IFCR_CHTIF1_Pos (2U) macro1255 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1382 #define DMA_IFCR_CHTIF1_Pos (2U) macro1383 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
