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Searched refs:DMA_CLLR_ULL (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h759 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
2994 … DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); in LL_DMA_ConfigLinkUpdate()
3352 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
3374 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
3396 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
3397 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h955 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
4765 …DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA… in LL_DMA_ConfigLinkUpdate()
5360 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
5390 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
5420 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
5421 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h944 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
4671 …DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA… in LL_DMA_ConfigLinkUpdate()
5126 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
5148 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
5170 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
5171 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma_ex.c4203 DMA_CLLR_UB2 | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4218 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4401 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4466 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4612 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
Dstm32u5xx_ll_dma.c1127 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1155 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
/hal_stm32-3.6.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c854 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
877 DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3830 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4012 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4077 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4223 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma_ex.c4205 DMA_CLLR_UB2 | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4220 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4403 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4468 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4614 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
Dstm32h5xx_ll_dma.c1069 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1097 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
/hal_stm32-3.6.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2356 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba52xx.h2940 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba54xx.h3123 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba55xx.h3123 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
/hal_stm32-3.6.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3995 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h562xx.h5752 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h563xx.h7836 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h573xx.h8271 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h6023 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u545xx.h6423 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u575xx.h6422 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u5f7xx.h6972 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u595xx.h6676 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u5a5xx.h7125 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u585xx.h6871 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u599xx.h6964 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro

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