1 /*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <soc.h>
8 #include <stm32_ll_bus.h>
9 #include <stm32_ll_pwr.h>
10 #include <stm32_ll_rcc.h>
11 #include <stm32_ll_system.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/sys/__assert.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include "stm32_hsem.h"
18
19 /* Macros to fill up prescaler values */
20 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
21 #define ahb_prescaler(v) fn_ahb_prescaler(v)
22
23 #define fn_ahb5_prescaler(v) LL_RCC_AHB5_DIV_ ## v
24 #define ahb5_prescaler(v) fn_ahb5_prescaler(v)
25
26 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
27 #define apb1_prescaler(v) fn_apb1_prescaler(v)
28
29 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
30 #define apb2_prescaler(v) fn_apb2_prescaler(v)
31
32 #define fn_apb7_prescaler(v) LL_RCC_APB7_DIV_ ## v
33 #define apb7_prescaler(v) fn_apb7_prescaler(v)
34
35 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK_FREQ
36 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler
37
get_bus_clock(uint32_t clock,uint32_t prescaler)38 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
39 {
40 return clock / prescaler;
41 }
42
43 /** @brief Verifies clock is part of active clock configuration */
enabled_clock(uint32_t src_clk)44 int enabled_clock(uint32_t src_clk)
45 {
46 if ((src_clk == STM32_SRC_SYSCLK) ||
47 (src_clk == STM32_SRC_HCLK1) ||
48 (src_clk == STM32_SRC_HCLK5) ||
49 (src_clk == STM32_SRC_PCLK1) ||
50 (src_clk == STM32_SRC_PCLK2) ||
51 (src_clk == STM32_SRC_PCLK7) ||
52 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
53 ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
54 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
55 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
56 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
57 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
58 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) {
59 return 0;
60 }
61
62 return -ENOTSUP;
63 }
64
stm32_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)65 static inline int stm32_clock_control_on(const struct device *dev,
66 clock_control_subsys_t sub_system)
67 {
68 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
69 volatile int temp;
70
71 ARG_UNUSED(dev);
72
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
74 /* Attempt to toggle a wrong periph clock bit */
75 return -ENOTSUP;
76 }
77
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
79 pclken->enr);
80 /* Delay after enabling the clock, to allow it to become active */
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
82 UNUSED(temp);
83
84 return 0;
85 }
86
stm32_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)87 static inline int stm32_clock_control_off(const struct device *dev,
88 clock_control_subsys_t sub_system)
89 {
90 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
91
92 ARG_UNUSED(dev);
93
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
95 /* Attempt to toggle a wrong periph clock bit */
96 return -ENOTSUP;
97 }
98
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
100 pclken->enr);
101
102 return 0;
103 }
104
stm32_clock_control_configure(const struct device * dev,clock_control_subsys_t sub_system,void * data)105 static inline int stm32_clock_control_configure(const struct device *dev,
106 clock_control_subsys_t sub_system,
107 void *data)
108 {
109 #if defined(STM32_SRC_CLOCK_MIN)
110 /* At least one alt src clock available */
111 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
112 int err;
113
114 ARG_UNUSED(dev);
115 ARG_UNUSED(data);
116
117 err = enabled_clock(pclken->bus);
118 if (err < 0) {
119 /* Attempt to configure a src clock not available or not valid */
120 return err;
121 }
122
123 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
124 STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
125 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
126 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
127 STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
128 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
129
130 return 0;
131 #else
132 /* No src clock available: Not supported */
133 return -ENOTSUP;
134 #endif
135 }
136
137 __unused
get_pllsrc_frequency(void)138 static uint32_t get_pllsrc_frequency(void)
139 {
140
141 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
142 return STM32_HSI_FREQ;
143 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
144 return STM32_HSE_FREQ;
145 }
146
147 __ASSERT(0, "No PLL Source configured");
148 return 0;
149 }
150
151 __unused
get_pllsrc(void)152 static uint32_t get_pllsrc(void)
153 {
154
155 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
156 return LL_RCC_PLL1SOURCE_HSI;
157 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
158 return LL_RCC_PLL1SOURCE_HSE;
159 }
160
161 __ASSERT(0, "No PLL Source configured");
162 return 0;
163 }
164
stm32_clock_control_get_subsys_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)165 static int stm32_clock_control_get_subsys_rate(const struct device *dev,
166 clock_control_subsys_t sub_system,
167 uint32_t *rate)
168 {
169 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
170 /*
171 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
172 * SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
173 * since it will be updated after clock configuration and hence
174 * more likely to contain actual clock speed
175 */
176 uint32_t ahb_clock = SystemCoreClock;
177 uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
178 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
179 uint32_t apb7_clock = get_bus_clock(ahb_clock, STM32_APB7_PRESCALER);
180 uint32_t ahb5_clock;
181
182 ARG_UNUSED(dev);
183
184 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
185 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */
186 ahb5_clock = get_bus_clock(ahb_clock * STM32_AHB_PRESCALER,
187 STM32_AHB5_PRESCALER);
188 } else {
189 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */
190 if (IS_ENABLED(STM32_AHB5_DIV)) {
191 ahb5_clock = ahb_clock * STM32_AHB_PRESCALER / 2;
192 } else {
193 ahb5_clock = ahb_clock * STM32_AHB_PRESCALER;
194 }
195
196 }
197
198 __ASSERT(ahb5_clock <= MHZ(32), "AHB5 clock frequency exceeds 32 MHz");
199
200 switch (pclken->bus) {
201 case STM32_CLOCK_BUS_AHB1:
202 case STM32_CLOCK_BUS_AHB2:
203 case STM32_CLOCK_BUS_AHB4:
204 case STM32_SRC_HCLK1:
205 *rate = ahb_clock;
206 break;
207 case STM32_CLOCK_BUS_AHB5:
208 case STM32_SRC_HCLK5:
209 *rate = ahb5_clock;
210 break;
211 case STM32_CLOCK_BUS_APB1:
212 case STM32_CLOCK_BUS_APB1_2:
213 case STM32_SRC_PCLK1:
214 *rate = apb1_clock;
215 break;
216 case STM32_CLOCK_BUS_APB2:
217 case STM32_SRC_PCLK2:
218 *rate = apb2_clock;
219 break;
220 case STM32_CLOCK_BUS_APB7:
221 case STM32_SRC_PCLK7:
222 *rate = apb7_clock;
223 break;
224 case STM32_SRC_SYSCLK:
225 *rate = SystemCoreClock * STM32_CORE_PRESCALER;
226 break;
227 #if defined(STM32_PLL_ENABLED)
228 case STM32_SRC_PLL1_P:
229 *rate = __LL_RCC_CALC_PLL1PCLK_FREQ(get_pllsrc_frequency(),
230 STM32_PLL_M_DIVISOR,
231 STM32_PLL_N_MULTIPLIER,
232 STM32_PLL_P_DIVISOR);
233 break;
234 case STM32_SRC_PLL1_Q:
235 *rate = __LL_RCC_CALC_PLL1QCLK_FREQ(get_pllsrc_frequency(),
236 STM32_PLL_M_DIVISOR,
237 STM32_PLL_N_MULTIPLIER,
238 STM32_PLL_Q_DIVISOR);
239 break;
240 case STM32_SRC_PLL1_R:
241 *rate = __LL_RCC_CALC_PLL1RCLK_FREQ(get_pllsrc_frequency(),
242 STM32_PLL_M_DIVISOR,
243 STM32_PLL_N_MULTIPLIER,
244 STM32_PLL_R_DIVISOR);
245 break;
246 #endif /* STM32_PLL_ENABLED */
247 #if defined(STM32_LSE_ENABLED)
248 case STM32_SRC_LSE:
249 *rate = STM32_LSE_FREQ;
250 break;
251 #endif
252 #if defined(STM32_LSI_ENABLED)
253 case STM32_SRC_LSI:
254 *rate = STM32_LSI_FREQ;
255 break;
256 #endif
257 #if defined(STM32_HSI_ENABLED)
258 case STM32_SRC_HSI16:
259 *rate = STM32_HSI_FREQ;
260 break;
261 #endif
262 #if defined(STM32_HSE_ENABLED)
263 case STM32_SRC_HSE:
264 if (IS_ENABLED(STM32_HSE_DIV2)) {
265 *rate = STM32_HSE_FREQ / 2;
266 } else {
267 *rate = STM32_HSE_FREQ;
268 }
269
270 break;
271 #endif
272 default:
273 return -ENOTSUP;
274 }
275
276 if (pclken->div) {
277 *rate /= (pclken->div + 1);
278 }
279
280 return 0;
281 }
282
stm32_clock_control_get_status(const struct device * dev,clock_control_subsys_t sub_system)283 static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
284 clock_control_subsys_t sub_system)
285 {
286 struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
287
288 ARG_UNUSED(dev);
289
290 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
291 /* Gated clocks */
292 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
293 == pclken->enr) {
294 return CLOCK_CONTROL_STATUS_ON;
295 } else {
296 return CLOCK_CONTROL_STATUS_OFF;
297 }
298 } else {
299 /* Domain clock sources */
300 if (enabled_clock(pclken->bus) == 0) {
301 return CLOCK_CONTROL_STATUS_ON;
302 } else {
303 return CLOCK_CONTROL_STATUS_OFF;
304 }
305 }
306 }
307
308 static DEVICE_API(clock_control, stm32_clock_control_api) = {
309 .on = stm32_clock_control_on,
310 .off = stm32_clock_control_off,
311 .get_rate = stm32_clock_control_get_subsys_rate,
312 .get_status = stm32_clock_control_get_status,
313 .configure = stm32_clock_control_configure,
314 };
315
316 __unused
get_vco_input_range(uint32_t m_div,uint32_t * range)317 static int get_vco_input_range(uint32_t m_div, uint32_t *range)
318 {
319 uint32_t vco_freq;
320
321 vco_freq = get_pllsrc_frequency() / m_div;
322
323 if (MHZ(4) <= vco_freq && vco_freq <= MHZ(8)) {
324 *range = LL_RCC_PLLINPUTRANGE_4_8;
325 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
326 *range = LL_RCC_PLLINPUTRANGE_8_16;
327 } else {
328 return -ERANGE;
329 }
330
331 return 0;
332 }
333
set_regu_voltage(uint32_t hclk_freq)334 static void set_regu_voltage(uint32_t hclk_freq)
335 {
336 if (hclk_freq <= MHZ(16)) {
337 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
338 } else {
339 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
340 }
341 while (LL_PWR_IsActiveFlag_VOS() == 0) {
342 }
343 }
344
345 /*
346 * Unconditionally switch the system clock source to HSI.
347 */
348 __unused
stm32_clock_switch_to_hsi(void)349 static void stm32_clock_switch_to_hsi(void)
350 {
351 /* Enable HSI if not enabled */
352 if (LL_RCC_HSI_IsReady() != 1) {
353 /* Enable HSI */
354 LL_RCC_HSI_Enable();
355 while (LL_RCC_HSI_IsReady() != 1) {
356 /* Wait for HSI ready */
357 }
358 }
359
360 /* Set HSI as SYSCLCK source */
361 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
362 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
363 }
364
365 /* Erratum 2.2.4: Spurious deactivation of HSE when HSI is selected as
366 * system clock source
367 * Re-enable HSE clock if required after switch source to HSI
368 */
369 if (IS_ENABLED(STM32_HSE_ENABLED)) {
370 if (IS_ENABLED(STM32_HSE_DIV2)) {
371 LL_RCC_HSE_EnablePrescaler();
372 }
373
374 /* Enable HSE */
375 LL_RCC_HSE_Enable();
376 while (LL_RCC_HSE_IsReady() != 1) {
377 /* Wait for HSE ready */
378 }
379 }
380 }
381
382 __unused
set_up_plls(void)383 static int set_up_plls(void)
384 {
385 #if defined(STM32_PLL_ENABLED)
386 int r;
387 uint32_t vco_input_range;
388
389 LL_RCC_PLL1_Disable();
390
391 /* Configure PLL source */
392 /* Can be HSE, HSI */
393 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
394 /* Main PLL configuration and activation */
395 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSE);
396 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
397 /* Main PLL configuration and activation */
398 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSI);
399 } else {
400 return -ENOTSUP;
401 }
402
403 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
404 if (r < 0) {
405 return r;
406 }
407
408 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR);
409
410 LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
411
412 LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
413
414 LL_RCC_PLL1FRACN_Disable();
415
416 if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
417 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
418 LL_RCC_PLL1_EnableDomain_PLL1P();
419 }
420
421 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
422 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
423 LL_RCC_PLL1_EnableDomain_PLL1Q();
424 }
425
426 if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
427 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
428
429 LL_RCC_PLL1_EnableDomain_PLL1R();
430 }
431
432 /* Enable PLL */
433 LL_RCC_PLL1_Enable();
434 while (LL_RCC_PLL1_IsReady() != 1U) {
435 /* Wait for PLL ready */
436 }
437 #else
438 /* Init PLL source to None */
439 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_NONE);
440 #endif /* STM32_PLL_ENABLED */
441
442 return 0;
443 }
444
set_up_fixed_clock_sources(void)445 static void set_up_fixed_clock_sources(void)
446 {
447
448 if (IS_ENABLED(STM32_HSE_ENABLED)) {
449 if (IS_ENABLED(STM32_HSE_DIV2)) {
450 LL_RCC_HSE_EnablePrescaler();
451 }
452
453 /* Enable HSE */
454 LL_RCC_HSE_Enable();
455 while (LL_RCC_HSE_IsReady() != 1) {
456 /* Wait for HSE ready */
457 }
458 }
459
460 if (IS_ENABLED(STM32_HSI_ENABLED)) {
461 /* Enable HSI if not enabled */
462 if (LL_RCC_HSI_IsReady() != 1) {
463 /* Enable HSI */
464 LL_RCC_HSI_Enable();
465 while (LL_RCC_HSI_IsReady() != 1) {
466 /* Wait for HSI ready */
467 }
468 }
469 }
470
471 if (IS_ENABLED(STM32_LSI_ENABLED)) {
472 /* LSI belongs to the back-up domain, enable access.*/
473
474 /* Set the DBP bit in the Power control register 1 (PWR_CR1) */
475 LL_PWR_EnableBkUpAccess();
476 while (!LL_PWR_IsEnabledBkUpAccess()) {
477 /* Wait for Backup domain access */
478 }
479
480 LL_RCC_LSI1_Enable();
481 while (LL_RCC_LSI1_IsReady() != 1) {
482 }
483
484 LL_PWR_DisableBkUpAccess();
485 }
486
487 if (IS_ENABLED(STM32_LSE_ENABLED)) {
488 /* LSE belongs to the back-up domain, enable access.*/
489
490 /* Set the DBP bit in the Power control register 1 (PWR_CR1) */
491 LL_PWR_EnableBkUpAccess();
492 while (!LL_PWR_IsEnabledBkUpAccess()) {
493 /* Wait for Backup domain access */
494 }
495
496 /* Configure driving capability */
497 LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR1_LSEDRV_Pos);
498
499 /* Enable LSE Oscillator (32.768 kHz) */
500 LL_RCC_LSE_Enable();
501 while (!LL_RCC_LSE_IsReady()) {
502 /* Wait for LSE ready */
503 }
504
505 /* Enable LSESYS additionally */
506 LL_RCC_LSE_EnablePropagation();
507 /* Wait till LSESYS is ready */
508 while (!LL_RCC_LSE_IsPropagationReady()) {
509 }
510 }
511 }
512
513 /**
514 * @brief Initialize clocks for the stm32
515 *
516 * This routine is called to enable and configure the clocks and PLL
517 * of the soc on the board. It depends on the board definition.
518 * This function is called on the startup and also to restore the config
519 * when exiting for low power mode.
520 *
521 * @param dev clock device struct
522 *
523 * @return 0
524 */
stm32_clock_control_init(const struct device * dev)525 int stm32_clock_control_init(const struct device *dev)
526 {
527 uint32_t old_flash_freq;
528 int r;
529
530 ARG_UNUSED(dev);
531
532 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL) &&
533 (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R)) {
534 /* In case of chainloaded application, it may happen that PLL
535 * was already configured as sysclk src by bootloader.
536 * Don't test other cases as there are multiple options but
537 * they will be handled smoothly by the function.
538 */
539 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
540 return 0;
541 }
542
543 old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(),
544 GET_CURRENT_FLASH_PRESCALER());
545
546 /* Set up individual enabled clocks */
547 set_up_fixed_clock_sources();
548
549 /* Set voltage regulator to comply with targeted system frequency */
550 set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
551
552 /* If required, apply max step freq for Sysclock w/ PLL input */
553 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
554 LL_RCC_PLL1_SetPLL1RCLKDivisionStep(LL_RCC_PLL1RCLK_2_STEP_DIV);
555
556 /* Send 2 pulses on CLKPRE like it is done in STM32Cube HAL */
557 LL_RCC_PLL1_DisablePLL1RCLKDivision();
558 LL_RCC_PLL1_EnablePLL1RCLKDivision();
559 LL_RCC_PLL1_DisablePLL1RCLKDivision();
560 LL_RCC_PLL1_EnablePLL1RCLKDivision();
561 }
562
563 /* Set up PLLs */
564 r = set_up_plls();
565 if (r < 0) {
566 return r;
567 }
568
569 /* If freq increases, set flash latency before any clock setting */
570 if (old_flash_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
571 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
572 }
573
574 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));
575
576 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
577 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */
578 LL_RCC_SetAHB5Prescaler(ahb5_prescaler(STM32_AHB5_PRESCALER));
579 } else {
580 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */
581 if (IS_ENABLED(STM32_AHB5_DIV)) {
582 LL_RCC_SetAHB5Divider(LL_RCC_AHB5_DIVIDER_2);
583 } else {
584 LL_RCC_SetAHB5Divider(LL_RCC_AHB5_DIVIDER_1);
585 }
586 }
587
588 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
589 /* Set PLL as System Clock Source */
590 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1R);
591 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R) {
592 }
593 LL_RCC_PLL1_DisablePLL1RCLKDivision();
594 while (LL_RCC_PLL1_IsPLL1RCLKDivisionReady() == 0) {
595 }
596 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
597 /* Set HSE as SYSCLCK source */
598 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
599 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
600 }
601 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
602 stm32_clock_switch_to_hsi();
603 }
604
605 /* If freq not increased, set flash latency after all clock setting */
606 if (old_flash_freq >= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
607 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
608 }
609
610 /* Set voltage regulator to comply with targeted system frequency */
611 set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
612
613 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
614
615 /* Set bus prescalers prescaler */
616 LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
617 LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
618 LL_RCC_SetAPB7Prescaler(apb7_prescaler(STM32_APB7_PRESCALER));
619
620 return 0;
621 }
622
623 /**
624 * @brief RCC device, note that priority is intentionally set to 1 so
625 * that the device init runs just after SOC init
626 */
627 DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
628 stm32_clock_control_init,
629 NULL,
630 NULL, NULL,
631 PRE_KERNEL_1,
632 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
633 &stm32_clock_control_api);
634
