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Searched refs:TSC_IOGCSR_G4S_Pos (Results 1 – 25 of 79) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5900 #define TSC_IOGCSR_G4S_Pos (19U) macro
5901 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f051x8.h5931 #define TSC_IOGCSR_G4S_Pos (19U) macro
5932 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f071xb.h6484 #define TSC_IOGCSR_G4S_Pos (19U) macro
6485 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f048xx.h9670 #define TSC_IOGCSR_G4S_Pos (19U) macro
9671 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f042x6.h9706 #define TSC_IOGCSR_G4S_Pos (19U) macro
9707 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f098xx.h10905 #define TSC_IOGCSR_G4S_Pos (19U) macro
10906 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f078xx.h10251 #define TSC_IOGCSR_G4S_Pos (19U) macro
10252 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f072xb.h10281 #define TSC_IOGCSR_G4S_Pos (19U) macro
10282 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f091xc.h10938 #define TSC_IOGCSR_G4S_Pos (19U) macro
10939 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
/hal_stm32-3.5.0/stm32cube/stm32l0xx/soc/
Dstm32l053xx.h6616 #define TSC_IOGCSR_G4S_Pos (19U) macro
6617 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l062xx.h6594 #define TSC_IOGCSR_G4S_Pos (19U) macro
6595 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l052xx.h6457 #define TSC_IOGCSR_G4S_Pos (19U) macro
6458 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l073xx.h6912 #define TSC_IOGCSR_G4S_Pos (19U) macro
6913 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l083xx.h7049 #define TSC_IOGCSR_G4S_Pos (19U) macro
7050 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l082xx.h6890 #define TSC_IOGCSR_G4S_Pos (19U) macro
6891 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l072xx.h6753 #define TSC_IOGCSR_G4S_Pos (19U) macro
6754 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32l063xx.h6751 #define TSC_IOGCSR_G4S_Pos (19U) macro
6752 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
/hal_stm32-3.5.0/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7718 #define TSC_IOGCSR_G4S_Pos (19U) macro
7719 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f318xx.h7705 #define TSC_IOGCSR_G4S_Pos (19U) macro
7706 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f373xc.h10892 #define TSC_IOGCSR_G4S_Pos (19U) macro
10893 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32f378xx.h10790 #define TSC_IOGCSR_G4S_Pos (19U) macro
10791 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9507 #define TSC_IOGCSR_G4S_Pos (19U) macro
9508 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb15xx.h8332 #define TSC_IOGCSR_G4S_Pos (19U) macro
8333 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Dstm32wb10xx.h8160 #define TSC_IOGCSR_G4S_Pos (19U) macro
8161 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8332 #define TSC_IOGCSR_G4S_Pos (19U) macro
8333 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */

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