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Searched refs:TSC_IOCCR_G5_IO2_Pos (Results 1 – 25 of 77) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5820 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
5821 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f051x8.h5851 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
5852 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f071xb.h6404 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6405 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f048xx.h9590 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
9591 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f042x6.h9626 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
9627 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f098xx.h10825 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10826 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f078xx.h10171 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10172 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f072xb.h10201 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10202 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f091xc.h10858 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10859 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-3.5.0/stm32cube/stm32l0xx/soc/
Dstm32l053xx.h6536 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6537 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l062xx.h6514 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6515 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l052xx.h6377 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6378 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l073xx.h6832 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6833 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l083xx.h6969 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6970 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l082xx.h6810 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6811 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l072xx.h6673 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6674 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l063xx.h6671 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
6672 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-3.5.0/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7638 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
7639 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f318xx.h7625 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
7626 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f373xc.h10812 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10813 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f378xx.h10710 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
10711 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9463 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
9464 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb15xx.h8267 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
8268 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32wb10xx.h8095 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
8096 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8267 #define TSC_IOCCR_G5_IO2_Pos (17U) macro
8268 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */

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