/hal_stm32-3.5.0/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5820 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 5821 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f051x8.h | 5851 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 5852 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f071xb.h | 6404 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6405 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f048xx.h | 9590 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 9591 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f042x6.h | 9626 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 9627 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f098xx.h | 10825 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10826 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f078xx.h | 10171 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10172 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f072xb.h | 10201 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10202 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f091xc.h | 10858 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10859 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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/hal_stm32-3.5.0/stm32cube/stm32l0xx/soc/ |
D | stm32l053xx.h | 6536 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6537 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l062xx.h | 6514 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6515 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l052xx.h | 6377 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6378 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l073xx.h | 6832 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6833 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l083xx.h | 6969 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6970 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l082xx.h | 6810 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6811 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l072xx.h | 6673 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6674 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32l063xx.h | 6671 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 6672 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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/hal_stm32-3.5.0/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7638 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 7639 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f318xx.h | 7625 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 7626 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f373xc.h | 10812 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10813 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32f378xx.h | 10710 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 10711 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9463 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 9464 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb15xx.h | 8267 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 8268 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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D | stm32wb10xx.h | 8095 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 8096 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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/hal_stm32-3.5.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8267 #define TSC_IOCCR_G5_IO2_Pos (17U) macro 8268 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
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