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Searched refs:PLL1P (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/boards/fanke/fk7b0m1_vbt6/
Dfk7b0m1_vbt6.dts56 /* PLL1P is used for system clock (280 MHz) */
/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts94 /* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5.dtsi745 * The SDMMC domain clock can be chosen between ICLK and PLL1P.