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Searched refs:NSBank (Results 1 – 25 of 53) sorted by relevance

123

/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_nor.c263 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
269 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
288 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
292 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
296 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
307 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
346 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
457 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
461 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_nor.c263 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
269 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
288 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
292 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
296 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
307 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
346 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
457 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
461 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32h7xx_hal_sram.c207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
214 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
247 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
954 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
988 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_nor.c264 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
267 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
270 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
286 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
290 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
294 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
305 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
344 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
455 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
459 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32f4xx_hal_sram.c202 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
205 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
209 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
239 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
946 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
980 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_hal_nor.c264 (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
267 …(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.E… in HAL_NOR_Init()
270 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
286 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Init()
290 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Init()
294 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) in HAL_NOR_Init()
305 (void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
344 (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
455 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
459 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32l1xx_hal_sram.c202 (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
205 (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
209 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
239 (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
946 (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
980 (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_nor.c264 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
267 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
270 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
286 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
290 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
294 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
305 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
344 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
455 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
459 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_nor.c263 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
269 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
285 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
289 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
293 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
304 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
343 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
454 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
458 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32f7xx_hal_sram.c201 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
204 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
208 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
238 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
945 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
979 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_nor.c263 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
269 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
285 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
289 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
293 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
304 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
343 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
454 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
458 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32l5xx_ll_fmc.c181 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
200 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
249 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
252 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
257 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
273 switch (Init->NSBank) in FMC_NORSRAM_Init()
Dstm32l5xx_hal_sram.c207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
214 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
244 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
951 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
985 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_nor.c263 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.Ex… in HAL_NOR_Init()
269 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
285 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
289 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
293 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
331 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
438 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
442 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
446 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Read_ID()
[all …]
Dstm32g4xx_ll_fmc.c186 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
205 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
254 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
257 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
262 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
278 switch (Init->NSBank) in FMC_NORSRAM_Init()
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_hal_nor.c263 (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
266 …(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.E… in HAL_NOR_Init()
269 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
285 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Init()
289 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Init()
293 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) in HAL_NOR_Init()
331 (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
438 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
442 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
446 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) in HAL_NOR_Read_ID()
[all …]
Dstm32f1xx_hal_sram.c202 (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
205 (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
209 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
239 (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
946 (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
980 (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_nor.c269 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
273 hnor->Init.NSBank, hnor->Init.ExtendedMode); in HAL_NOR_Init()
276 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
292 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
296 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
300 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
311 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
359 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
470 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
474 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32f3xx_hal_sram.c208 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
211 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
215 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
245 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
952 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
986 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_nor.c268 (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
272 hnor->Init.NSBank, hnor->Init.ExtendedMode); in HAL_NOR_Init()
275 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
291 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Init()
295 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Init()
299 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) in HAL_NOR_Init()
310 (void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
358 (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
469 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
473 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32f2xx_hal_sram.c207 (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
210 (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
214 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
244 (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
941 (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
975 (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_nor.c268 (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
272 hnor->Init.NSBank, hnor->Init.ExtendedMode); in HAL_NOR_Init()
275 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
294 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
298 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Init()
302 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) in HAL_NOR_Init()
313 (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); in HAL_NOR_Init()
361 (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); in HAL_NOR_DeInit()
472 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
476 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) in HAL_NOR_Read_ID()
[all …]
Dstm32u5xx_ll_fmc.c182 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
201 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
250 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
253 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
258 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
274 switch (Init->NSBank) in FMC_NORSRAM_Init()
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_sram.c206 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
209 …(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Ini… in HAL_SRAM_Init()
212 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
245 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
942 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
976 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
Dstm32mp1xx_ll_fmc.c164 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
182 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
194 MODIFY_REG(Device->BTCR[Init->NSBank], in FMC_NORSRAM_Init()
228 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
243 switch (Init->NSBank) in FMC_NORSRAM_Init()

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