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Searched refs:TSC_IOGCSR_G5E_Pos (Results 1 – 25 of 69) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32f0xx/soc/
Dstm32f051x8.h5910 #define TSC_IOGCSR_G5E_Pos (4U) macro
5911 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f058xx.h5879 #define TSC_IOGCSR_G5E_Pos (4U) macro
5880 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f071xb.h6463 #define TSC_IOGCSR_G5E_Pos (4U) macro
6464 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f042x6.h9685 #define TSC_IOGCSR_G5E_Pos (4U) macro
9686 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f048xx.h9649 #define TSC_IOGCSR_G5E_Pos (4U) macro
9650 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f091xc.h10917 #define TSC_IOGCSR_G5E_Pos (4U) macro
10918 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f078xx.h10230 #define TSC_IOGCSR_G5E_Pos (4U) macro
10231 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f098xx.h10884 #define TSC_IOGCSR_G5E_Pos (4U) macro
10885 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f072xb.h10260 #define TSC_IOGCSR_G5E_Pos (4U) macro
10261 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
/hal_stm32-3.4.0/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6436 #define TSC_IOGCSR_G5E_Pos (4U) macro
6437 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l053xx.h6595 #define TSC_IOGCSR_G5E_Pos (4U) macro
6596 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l062xx.h6573 #define TSC_IOGCSR_G5E_Pos (4U) macro
6574 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l072xx.h6732 #define TSC_IOGCSR_G5E_Pos (4U) macro
6733 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l083xx.h7028 #define TSC_IOGCSR_G5E_Pos (4U) macro
7029 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l073xx.h6891 #define TSC_IOGCSR_G5E_Pos (4U) macro
6892 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l082xx.h6869 #define TSC_IOGCSR_G5E_Pos (4U) macro
6870 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32l063xx.h6730 #define TSC_IOGCSR_G5E_Pos (4U) macro
6731 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
/hal_stm32-3.4.0/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7697 #define TSC_IOGCSR_G5E_Pos (4U) macro
7698 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f318xx.h7684 #define TSC_IOGCSR_G5E_Pos (4U) macro
7685 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f373xc.h10871 #define TSC_IOGCSR_G5E_Pos (4U) macro
10872 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f378xx.h10769 #define TSC_IOGCSR_G5E_Pos (4U) macro
10770 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32f302xc.h11610 #define TSC_IOGCSR_G5E_Pos (4U) macro
11611 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
/hal_stm32-3.4.0/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8314 #define TSC_IOGCSR_G5E_Pos (4U) macro
8315 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
/hal_stm32-3.4.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8142 #define TSC_IOGCSR_G5E_Pos (4U) macro
8143 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Dstm32wb15xx.h8314 #define TSC_IOGCSR_G5E_Pos (4U) macro
8315 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */

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