/hal_stm32-3.4.0/stm32cube/stm32f0xx/soc/ |
D | stm32f051x8.h | 5910 #define TSC_IOGCSR_G5E_Pos (4U) macro 5911 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f058xx.h | 5879 #define TSC_IOGCSR_G5E_Pos (4U) macro 5880 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f071xb.h | 6463 #define TSC_IOGCSR_G5E_Pos (4U) macro 6464 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f042x6.h | 9685 #define TSC_IOGCSR_G5E_Pos (4U) macro 9686 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f048xx.h | 9649 #define TSC_IOGCSR_G5E_Pos (4U) macro 9650 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f091xc.h | 10917 #define TSC_IOGCSR_G5E_Pos (4U) macro 10918 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f078xx.h | 10230 #define TSC_IOGCSR_G5E_Pos (4U) macro 10231 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f098xx.h | 10884 #define TSC_IOGCSR_G5E_Pos (4U) macro 10885 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f072xb.h | 10260 #define TSC_IOGCSR_G5E_Pos (4U) macro 10261 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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/hal_stm32-3.4.0/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6436 #define TSC_IOGCSR_G5E_Pos (4U) macro 6437 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l053xx.h | 6595 #define TSC_IOGCSR_G5E_Pos (4U) macro 6596 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l062xx.h | 6573 #define TSC_IOGCSR_G5E_Pos (4U) macro 6574 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l072xx.h | 6732 #define TSC_IOGCSR_G5E_Pos (4U) macro 6733 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l083xx.h | 7028 #define TSC_IOGCSR_G5E_Pos (4U) macro 7029 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l073xx.h | 6891 #define TSC_IOGCSR_G5E_Pos (4U) macro 6892 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l082xx.h | 6869 #define TSC_IOGCSR_G5E_Pos (4U) macro 6870 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32l063xx.h | 6730 #define TSC_IOGCSR_G5E_Pos (4U) macro 6731 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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/hal_stm32-3.4.0/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7697 #define TSC_IOGCSR_G5E_Pos (4U) macro 7698 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f318xx.h | 7684 #define TSC_IOGCSR_G5E_Pos (4U) macro 7685 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f373xc.h | 10871 #define TSC_IOGCSR_G5E_Pos (4U) macro 10872 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f378xx.h | 10769 #define TSC_IOGCSR_G5E_Pos (4U) macro 10770 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32f302xc.h | 11610 #define TSC_IOGCSR_G5E_Pos (4U) macro 11611 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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/hal_stm32-3.4.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8314 #define TSC_IOGCSR_G5E_Pos (4U) macro 8315 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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/hal_stm32-3.4.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 8142 #define TSC_IOGCSR_G5E_Pos (4U) macro 8143 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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D | stm32wb15xx.h | 8314 #define TSC_IOGCSR_G5E_Pos (4U) macro 8315 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
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