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Searched refs:TIM_ECR_FIDX_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c3073 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
3082 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
3091 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c3006 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-3.4.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3261 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-3.4.0/stm32cube/stm32g4xx/soc/
Dstm32g431xx.h10813 #define TIM_ECR_FIDX_Pos (5U) macro
10814 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g441xx.h11043 #define TIM_ECR_FIDX_Pos (5U) macro
11044 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32gbk1cb.h10785 #define TIM_ECR_FIDX_Pos (5U) macro
10786 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g473xx.h12114 #define TIM_ECR_FIDX_Pos (5U) macro
12115 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g471xx.h11546 #define TIM_ECR_FIDX_Pos (5U) macro
11547 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g491xx.h11323 #define TIM_ECR_FIDX_Pos (5U) macro
11324 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g4a1xx.h11553 #define TIM_ECR_FIDX_Pos (5U) macro
11554 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g483xx.h12344 #define TIM_ECR_FIDX_Pos (5U) macro
12345 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g474xx.h15693 #define TIM_ECR_FIDX_Pos (5U) macro
15694 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g484xx.h15923 #define TIM_ECR_FIDX_Pos (5U) macro
15924 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7913 #define TIM_ECR_FIDX_Pos (5U) macro
7914 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32h562xx.h10599 #define TIM_ECR_FIDX_Pos (5U) macro
10600 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32h563xx.h12683 #define TIM_ECR_FIDX_Pos (5U) macro
12684 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32h573xx.h13094 #define TIM_ECR_FIDX_Pos (5U) macro
13095 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h10650 #define TIM_ECR_FIDX_Pos (5U) macro
10651 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u545xx.h11050 #define TIM_ECR_FIDX_Pos (5U) macro
11051 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u575xx.h11673 #define TIM_ECR_FIDX_Pos (5U) macro
11674 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u585xx.h12122 #define TIM_ECR_FIDX_Pos (5U) macro
12123 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u5a5xx.h12430 #define TIM_ECR_FIDX_Pos (5U) macro
12431 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u595xx.h11981 #define TIM_ECR_FIDX_Pos (5U) macro
11982 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u599xx.h15700 #define TIM_ECR_FIDX_Pos (5U) macro
15701 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32u5a9xx.h16149 #define TIM_ECR_FIDX_Pos (5U) macro
16150 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…