Searched refs:TIM1_AF1_ETRSEL_3 (Results 1 – 25 of 97) sorted by relevance
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119 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3) /*!…120 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!…121 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…122 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…123 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!…124 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!…126 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!…139 #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!…140 #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!…141 #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…[all …]
1041 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 …1042 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) …1043 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1044 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1045 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) …1046 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_…1048 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_…1067 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 …1068 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) …1069 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …[all …]
121 #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /* !< …122 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< …123 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< …125 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< …126 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< …127 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< …144 #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< …145 #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< …147 #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< …149 #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !<…[all …]
1036 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 …1037 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) …1038 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1040 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1041 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) …1042 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_…1065 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 …1066 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) …1068 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1070 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL…[all …]
126 #define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) /*!…128 #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) /*!…131 #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!…134 #define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!…141 #define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!…143 #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…146 #define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!…149 #define TIM_TIM3_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!…154 #define TIM_TIM4_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!…155 #define TIM_TIM4_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!…[all …]
1057 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) …1059 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) …1062 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3…1065 …PS (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR i…1078 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 …1080 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1083 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0…1086 …PS (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR i…1097 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 …1098 #define LL_TIM_TIM4_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) …[all …]
96 #define TIM_TIM1_ETR_ADC2_AWD3 TIM1_AF1_ETRSEL_3 /* !< …
937 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3) …945 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3) …
99 #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< T…
990 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 …
5825 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
5985 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
6444 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
6505 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
6644 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
6708 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7012 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7107 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7411 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7821 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7795 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
7491 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
9386 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
11058 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro