Home
last modified time | relevance | path

Searched refs:CFG2 (Results 1 – 25 of 97) sorted by relevance

1234

/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_spi.h667 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_EnableIOSwap()
679 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_DisableIOSwap()
690 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); in LL_SPI_IsEnabledIOSwap()
702 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_EnableGPIOControl()
714 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_DisableGPIOControl()
725 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); in LL_SPI_IsEnabledGPIOControl()
740 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); in LL_SPI_SetMode()
753 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); in LL_SPI_GetMode()
781 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); in LL_SPI_SetMasterSSIdleness()
808 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); in LL_SPI_GetMasterSSIdleness()
[all …]
Dstm32u5xx_ll_ucpd.h464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterEnable()
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterDisable()
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable()
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpDisable()
508 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable()
519 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockDisable()
530 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterEnable()
541 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable()
Dstm32u5xx_hal_spi.h920 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
927 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
934 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_spi.h592 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_EnableIOSwap()
604 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_DisableIOSwap()
615 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); in LL_SPI_IsEnabledIOSwap()
627 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_EnableGPIOControl()
639 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_DisableGPIOControl()
650 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); in LL_SPI_IsEnabledGPIOControl()
665 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); in LL_SPI_SetMode()
678 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); in LL_SPI_GetMode()
706 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); in LL_SPI_SetMasterSSIdleness()
733 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); in LL_SPI_GetMasterSSIdleness()
[all …]
Dstm32h7xx_hal_spi.h947 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
954 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
961 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_spi.h592 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_EnableIOSwap()
604 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_DisableIOSwap()
615 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); in LL_SPI_IsEnabledIOSwap()
627 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_EnableGPIOControl()
639 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_DisableGPIOControl()
650 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); in LL_SPI_IsEnabledGPIOControl()
665 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); in LL_SPI_SetMode()
678 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); in LL_SPI_GetMode()
706 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); in LL_SPI_SetMasterSSIdleness()
733 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); in LL_SPI_GetMasterSSIdleness()
[all …]
Dstm32mp1xx_hal_spi.h947 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
954 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
961 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_spi.h580 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_EnableIOSwap()
592 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); in LL_SPI_DisableIOSwap()
603 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); in LL_SPI_IsEnabledIOSwap()
615 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_EnableGPIOControl()
627 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); in LL_SPI_DisableGPIOControl()
638 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); in LL_SPI_IsEnabledGPIOControl()
653 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); in LL_SPI_SetMode()
666 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); in LL_SPI_GetMode()
694 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); in LL_SPI_SetMasterSSIdleness()
721 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); in LL_SPI_GetMasterSSIdleness()
[all …]
Dstm32h5xx_ll_ucpd.h464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterEnable()
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterDisable()
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable()
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpDisable()
508 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable()
519 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockDisable()
530 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterEnable()
541 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable()
Dstm32h5xx_hal_spi.h920 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
927 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_…
934 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
/hal_stm32-3.4.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_ucpd.h464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable()
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpDisable()
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable()
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockDisable()
508 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterEnable()
519 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable()
/hal_stm32-3.4.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_ucpd.h464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable()
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpDisable()
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable()
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockDisable()
508 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterEnable()
519 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable()
/hal_stm32-3.4.0/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_ucpd.h464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable()
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpDisable()
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable()
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockDisable()
508 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterEnable()
519 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable()
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_spi.c392 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | in LL_SPI_Init()
Dstm32u5xx_hal_spi.c412 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | in HAL_SPI_Init()
478 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); in HAL_SPI_Init()
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_i2s.c447 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit); in HAL_I2S_Init()
453 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState)); in HAL_I2S_Init()
Dstm32h7xx_ll_spi.c392 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | in LL_SPI_Init()
Dstm32h7xx_hal_spi.c394 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | in HAL_SPI_Init()
464 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); in HAL_SPI_Init()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_i2s.c438 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit); in HAL_I2S_Init()
444 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState)); in HAL_I2S_Init()
Dstm32h5xx_ll_spi.c393 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | in LL_SPI_Init()
Dstm32h5xx_hal_spi.c412 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | in HAL_SPI_Init()
478 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); in HAL_SPI_Init()
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_spi.c395 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | in LL_SPI_Init()
Dstm32mp1xx_hal_spi.c394 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | in HAL_SPI_Init()
464 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); in HAL_SPI_Init()
/hal_stm32-3.4.0/stm32cube/stm32g0xx/soc/
Dstm32g081xx.h655 …__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 … member
Dstm32g071xx.h613 …__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 … member

1234