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Searched refs:RI_CICR4_PF_Pos (Results 1 – 16 of 16) sorted by relevance

/hal_stm32-2.7.6/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h6211 #define RI_CICR4_PF_Pos (0U) macro
6212 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6214 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6215 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6216 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6217 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6218 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6219 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6220 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6221 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xdx.h6818 #define RI_CICR4_PF_Pos (0U) macro
6819 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6821 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6822 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6823 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6824 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6825 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6826 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6827 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6828 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xdx.h6679 #define RI_CICR4_PF_Pos (0U) macro
6680 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6682 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6683 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6684 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6685 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6686 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6687 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6688 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6689 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xe.h6679 #define RI_CICR4_PF_Pos (0U) macro
6680 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6682 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6683 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6684 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6685 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6686 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6687 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6688 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6689 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xe.h6818 #define RI_CICR4_PF_Pos (0U) macro
6819 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6821 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6822 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6823 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6824 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6825 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6826 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6827 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6828 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xc.h6668 #define RI_CICR4_PF_Pos (0U) macro
6669 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6671 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6672 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6673 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6674 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6675 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6676 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6677 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6678 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xca.h6753 #define RI_CICR4_PF_Pos (0U) macro
6754 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6756 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6757 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6758 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6759 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6760 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6761 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6762 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6763 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xc.h6379 #define RI_CICR4_PF_Pos (0U) macro
6380 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6382 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6383 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6384 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6385 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6386 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6387 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6388 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6389 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xca.h6464 #define RI_CICR4_PF_Pos (0U) macro
6465 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6467 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6468 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6469 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6470 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6471 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6472 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6473 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6474 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xe.h6529 #define RI_CICR4_PF_Pos (0U) macro
6530 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6532 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6533 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6534 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6535 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6536 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6537 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6538 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6539 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xc.h6529 #define RI_CICR4_PF_Pos (0U) macro
6530 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6532 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6533 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6534 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6535 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6536 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6537 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6538 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6539 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xca.h6614 #define RI_CICR4_PF_Pos (0U) macro
6615 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6617 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6618 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6619 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6620 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6621 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6622 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6623 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6624 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xdx.h6529 #define RI_CICR4_PF_Pos (0U) macro
6530 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6532 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6533 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6534 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6535 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6536 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6537 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6538 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6539 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xd.h7314 #define RI_CICR4_PF_Pos (0U) macro
7315 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7317 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7318 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7319 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7320 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7321 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7322 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7323 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7324 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xd.h7164 #define RI_CICR4_PF_Pos (0U) macro
7165 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7167 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7168 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7169 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7170 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7171 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7172 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7173 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7174 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xd.h7453 #define RI_CICR4_PF_Pos (0U) macro
7454 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7456 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7457 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7458 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7459 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7460 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7461 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7462 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7463 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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