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Searched refs:RCC (Results 1 – 25 of 382) sorted by relevance

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/hal_stm32-2.7.6/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_rcc.h948 #define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY )
949 #define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY )
950 #define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY )
951 #define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY )
952 #define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY )
953 #define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST )
956 #define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MP…
959 #define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_A…
962 #define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_M…
965 #define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_P…
[all …]
Dstm32mp1xx_ll_rcc.h38 #if defined(RCC)
1325 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1332 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1474 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSECSSON); in LL_RCC_HSE_EnableCSS()
1485 WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_DIGBYP); in LL_RCC_HSE_EnableDigBypass()
1486 WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSEBYP); in LL_RCC_HSE_EnableDigBypass()
1496 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_DIGBYP); in LL_RCC_HSE_DisableDigBypass()
1497 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEBYP); in LL_RCC_HSE_DisableDigBypass()
1507 WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSEBYP); in LL_RCC_HSE_EnableBypass()
1517 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEBYP); in LL_RCC_HSE_DisableBypass()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h974 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
976 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
981 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
983 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
995 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
997 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1002 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1004 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
[all …]
Dstm32f4xx_hal_rcc.h388 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
390 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
395 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
397 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
402 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
404 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
409 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
411 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
416 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
418 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h675 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
677 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
682 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
684 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
689 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
691 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
696 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
698 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
703 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
705 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32u5xx_ll_rcc.h34 #if defined(RCC)
1000 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1007 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1282 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
1292 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
1302 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass()
1312 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
1322 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
1332 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); in LL_RCC_HSE_IsReady()
1346 MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode); in LL_RCC_HSE_SetClockMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h503 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
505 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
511 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
513 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
519 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
521 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
527 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
529 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
535 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
537 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
428 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
430 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
442 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
444 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h641 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
643 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
649 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
651 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
658 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
660 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
667 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
669 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
675 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
677 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h591 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
593 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
599 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
601 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
607 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
609 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
615 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
617 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
623 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
625 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
658 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
666 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
674 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
679 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
681 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
687 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
689 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
/hal_stm32-2.7.6/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h829 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
831 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
838 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
840 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
849 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
851 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
857 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
859 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
866 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
868 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h585 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
587 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
590 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
592 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U)
593 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U)
600 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
602 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
605 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
607 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U)
608 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U)
[all …]
Dstm32l0xx_hal_rcc.h680 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
682 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
688 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
690 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
696 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
703 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
704 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
705 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
720 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
[all …]
Dstm32l0xx_ll_rcc.h35 #if defined(RCC)
556 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
563 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
686 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
697 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
707 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass()
717 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
727 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
737 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); in LL_RCC_HSE_IsReady()
752 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); in LL_RCC_SetRTC_HSEPrescaler()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h645 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
647 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
652 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
654 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
659 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
661 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
666 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
668 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
673 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
675 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h769 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
771 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
777 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
779 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
786 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
788 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
795 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
797 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
804 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
806 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h631 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
633 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
637 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
644 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
646 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
650 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
656 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
658 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
663 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
669 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
[all …]
Dstm32f1xx_hal_rcc.h325 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
327 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
333 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
335 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
341 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
343 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
349 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
351 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
355 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
356 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h1806 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
1807 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource_…
1827 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource_…
1853 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
1858 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
1878 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1880 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1884 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
1891 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1893 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
[all …]
Dstm32f3xx_hal_rcc.h684 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
686 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
691 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
693 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
698 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
700 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
705 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
707 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
712 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
714 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h624 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
626 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
631 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
633 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
638 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
640 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
645 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
647 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
652 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
654 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
[all …]
/hal_stm32-2.7.6/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_rcc.h35 #if defined(RCC)
841 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
848 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1268 SET_BIT(RCC->CR, RCC_CR_HSEPRE); in LL_RCC_HSE_EnableDiv2()
1278 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE); in LL_RCC_HSE_DisableDiv2()
1288 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); in LL_RCC_HSE_IsEnabledDiv2()
1298 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
1308 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
1318 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
1328 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); in LL_RCC_HSE_IsReady()
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/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h51 #if defined(RCC)
290 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
292 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
311 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
329 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
348 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
367 CLEAR_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
386 SET_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
388 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
407 return ((READ_BIT(RCC->AHB1SMENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClockSleep()
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Dstm32wlxx_ll_rcc.h35 #if defined(RCC)
654 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
661 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
971 SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); in LL_RCC_HSE_EnableTcxo()
981 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); in LL_RCC_HSE_DisableTcxo()
991 return ((READ_BIT(RCC->CR, RCC_CR_HSEBYPPWR) == (RCC_CR_HSEBYPPWR)) ? 1UL : 0UL); in LL_RCC_HSE_IsEnabledTcxo()
1002 SET_BIT(RCC->CR, RCC_CR_HSEPRE); in LL_RCC_HSE_EnableDiv2()
1012 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE); in LL_RCC_HSE_DisableDiv2()
1022 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); in LL_RCC_HSE_IsEnabledDiv2()
1032 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
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