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Searched refs:DMA2D_CR_CAEIE (Results 1 – 25 of 57) sorted by relevance

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/hal_stm32-2.7.6/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma2d.h362 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
1688 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_EnableIT_CAE()
1754 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_DisableIT_CAE()
1820 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledIT_CAE()
Dstm32f4xx_hal_dma2d.h261 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
/hal_stm32-2.7.6/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_dma2d.h343 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
1941 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_EnableIT_CAE()
2007 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_DisableIT_CAE()
2073 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledIT_CAE()
Dstm32l4xx_hal_dma2d.h317 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
/hal_stm32-2.7.6/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma2d.h390 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
1904 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_EnableIT_CAE()
1970 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_DisableIT_CAE()
2036 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledIT_CAE()
Dstm32f7xx_hal_dma2d.h297 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma2d.h395 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
1973 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_EnableIT_CAE()
2039 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_DisableIT_CAE()
2105 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledIT_CAE()
Dstm32u5xx_hal_dma2d.h311 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
/hal_stm32-2.7.6/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma2d.h402 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
2018 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_EnableIT_CAE()
2084 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); in LL_DMA2D_DisableIT_CAE()
2150 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledIT_CAE()
Dstm32h7xx_hal_dma2d.h324 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
/hal_stm32-2.7.6/stm32cube/stm32f4xx/soc/
Dstm32f437xx.h6505 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f427xx.h6313 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f429xx.h6372 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f439xx.h6559 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
/hal_stm32-2.7.6/stm32cube/stm32f7xx/soc/
Dstm32f746xx.h6450 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f756xx.h6638 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f750xx.h6638 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f745xx.h6395 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f765xx.h6855 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f777xx.h7137 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32f767xx.h6949 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
/hal_stm32-2.7.6/stm32cube/stm32l4xx/soc/
Dstm32l4s7xx.h7986 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32l496xx.h7517 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32l4a6xx.h7762 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro
Dstm32l4s5xx.h7900 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Err… macro

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