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/hal_silabs-latest/scripts/
Dgen_acmp.py48 with bits_file.open() as f:
49 for line in f:
53 input_name = f"#define ACMP_INPUT_{m.group(1).split('_')[-1]}"
57 … print(f"Inputs {input_name} and {defines[input_value]} share the same value {input_value}.")
58 defines.update({input_value : f"{input_name} {input_value}"})
62 input_name = f"#define ACMP_INPUT_{m.group(1).split('_')[-1]}"
66 … print(f"Inputs {input_name} and {defines[input_value]} share the same value {input_value}.")
67 defines.update({input_value : f"{input_name} {input_value}"})
74 f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.",
78 f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.",
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Dgen_clock_control.py62 print(f"Generate clock control binding for {device}")
65 with bits_file.open() as f:
66 for line in f:
73 with node_file.open() as f:
74 for line in f:
77 nodes.append(f"#define {m.group(1)}"
78 f"{' ' * (20 - len(m.group(1)))}"
79 f"(FIELD_PREP(CLOCK_REG_MASK, {clocks[m.group(2)]}) | "
80 f"FIELD_PREP(CLOCK_BIT_MASK, {bits[m.group(3)]}))"
83 print(f"WARN: Failed to emit clock node: {e}")
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Dgen_pinctrl.py144 return f"{self.peripheral.name}_{self.name}"
170 print(f"Skipping download of CMSIS Pack for {family}, already exists")
172 print(f"Downloading CMSIS Pack for {family}")
183 print(f"Parsing SVD for {svd_path.stem}")
202 signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal)
210 signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal)
220 print(f"Parsing Pin Tool for {pin_tool.parent.stem}")
221 with open(pin_tool, 'r') as f:
222 tree = lxml.etree.parse(f)
229 pt_peripheral = f"PRS.{signal.name}"
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Dgen_adc.py93 assert values[key] == val, f"{key} = {values[key]} from a previous device, new value = {val}"
116 print(f"Parse ADC data for {device}")
118 with (args.sdk / data_source["bits"]).open() as f:
119 for line in f:
130 insert(values, f"P{port[4]}{pin}", port_base + pin)
136 f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.",
140 f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.",
144 f"#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_",
145 f"#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_",
151 file.append(f"#define IADC_INPUT_{k}{' ' * (max_key - len(k) + 1)}0x{v:x}")
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Dimport_simplicity_sdk.py83 for f in src.glob(path):
84 destfile = dst / f.relative_to(src)
86 shutil.copy(f, destfile)
106 lfs = subprocess.check_output(["git", "show", f"HEAD:{str(path)}"], cwd=sdk).decode()
110 … blob["url"] = f"https://artifacts.silabs.net/artifactory/gsdk/objects/{sha[0:2]}/{sha[2:4]}/{sha}"
127 print(f"Import SDK from {src}")
134 print(f"Update module.yml with blobs from {src}")
Dimport_wiseconnect.py184 for f in src.glob(path):
185 if not os.path.exists(f):
186 print(f"Invalid path: {f}")
188 destfile = dst / f.relative_to(src)
191 print(f"Import {f.relative_to(src)}")
193 shutil.copy(f, destfile)
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_cmu.c4020 uint32_t f = 0U; in em01GrpbClkGet() local
4024 f = SystemHFRCODPLLClockGet(); in em01GrpbClkGet()
4029 f = SystemHFRCODPLLClockGet(); in em01GrpbClkGet()
4034 f = SystemHFXOClockGet(); in em01GrpbClkGet()
4039 f = SystemHFXOClockGet(); in em01GrpbClkGet()
4044 f = SystemFSRCOClockGet(); in em01GrpbClkGet()
4049 f = SystemCLKIN0Get(); in em01GrpbClkGet()
4063 *freq = f; in em01GrpbClkGet()
4121 uint32_t f = 0U; in eusart0ClkGet() local
4127 em01GrpaClkGet(&f, NULL); in eusart0ClkGet()
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/hal_silabs-latest/gecko/emlib/src/
Dem_cmu.c3969 uint32_t f = 0U; in em01GrpbClkGet() local
3973 f = SystemHFRCODPLLClockGet(); in em01GrpbClkGet()
3978 f = SystemHFRCODPLLClockGet(); in em01GrpbClkGet()
3983 f = SystemHFXOClockGet(); in em01GrpbClkGet()
3988 f = SystemHFXOClockGet(); in em01GrpbClkGet()
3993 f = SystemFSRCOClockGet(); in em01GrpbClkGet()
3998 f = SystemCLKIN0Get(); in em01GrpbClkGet()
4012 *freq = f; in em01GrpbClkGet()
4070 uint32_t f = 0U; in eusart0ClkGet() local
4076 em01GrpaClkGet(&f, NULL); in eusart0ClkGet()
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